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參數(shù)資料
型號: ICS301MT
英文描述: QTClock⑩ Quick Turn Clock Synthesizer
中文描述: QTClock⑩快速打開時鐘合成器
文件頁數(shù): 1/4頁
文件大小: 64K
代理商: ICS301MT
MDS 300QT E
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA95126(408) 295-9800tel www.icst.com
1
Revision 111000
ICS300/ICS301/ICS302
QTClock Quick Turn Clock Synthesizer
Packaged as 8 pin SOIC
Quick turn frequency programming allows
samples in one to three days
Replaces nearly any crystal or oscillator
ICS300 produces up to 100 MHz at 3.3V,
ICS301 produces up to 200 MHz at 3.3V
ICS302 accepts up to 125 MHz clock input
Easy to cascade with ICS5xx series
Input crystal frequency of 5 - 27 MHz
Input clock frequency of 2 - 125 MHz
Low jitter - 50 ps one sigma
Compatible with all popular CPUs
Duty cycle of 45/55
Operating voltages of 3.0 to 5.5V
Full CMOS level outputs with 25mA drive
capability at TTL levels
Tri-state output + PLL power down pin
Advanced, low power CMOS process
The ICS300 and ICS301 QTClocks generate a
high quality, high frequency clock output and a
reference from a low frequency crystal or clock
input. They are designed to replace crystals and
crystal oscillators in most electronic systems. The
ICS302 can accept a higher frequency clock input
to generate up to 200 MHz. The devices contain a
One Time Programmable (OTP) ROM which is
factory programmed with the PLL divider values
to output a broad range of frequencies, from 6 to
200 MHz, allowing customer requests for different
frequencies to be shipped in 1-3 days. Using
Phase-Locked-Loop (PLL) techniques, the devices
run from a standard fundamental mode,
inexpensive crystal, or clock. They are smaller and
less expensive than one oscillator.
Block Diagram
Description
Features
CLK
Crystal
Oscillator
VDD
GND
PLL
Clock
Synthesis
and Control
Circuitry
Output
Buffer
Crystal
or clock
input
REF
X2
X1/ICLK
Divide
Logic and
Output
Buffer
PDTS (both outputs and PLL)
OTP
ROM
with PLL
Divider
Values
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICS302M 制造商:ICS 制造商全稱:ICS 功能描述:QTClock⑩ Quick Turn Clock Synthesizer
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