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參數資料
| 型號： | ICS543MT |
| 英文描述： | PRELIMINARY INFORMATION Clock Divider and 2X Multiplier |
| 中文描述： | 初步資料2倍時鐘分頻器和乘法器 |
| 文件頁數： | 1/4頁 |
| 文件大小： | 60K |
| 代理商： | ICS543MT |
ICS543
Clock Divider and 2X Multiplier
MDS 543 A
Integrated Circuit Systems, Inc.525 Race StreetSan JoseCA95126(408)295-9800tel(408)295-9818fax
1
Revision 010599
Printed 12/4/00
ICRO
C
LOC K
PRELIMINARY INFORMATION
Packaged in 8 pin SOIC
Low cost clock divider and 2X multiplier
Low skew (500ps) outputs. One is ÷ 2 of other.
Easy to use with other generators and buffers
Input clock frequency up to 90 MHz at 5 V
Output clock duty cycle of 45/55
Power Down turns off chip
Output Enable
Full CMOS clock swings with 25 mA drive
capability at TTL levels
Advanced, low power CMOS process
Operating voltages of 3.0 to 5.5 V
The ICS543 is a cost effective way to produce a
high quality clock output divided from a clock
input. The chip accepts a clock input up to
90 MHz at 5.0 V, and by using proprietary Phase
Locked Loop (PLL) techniques, produces a divide
by 3, 5, 6, or 10, or a multiply by 2 of the input
clock. There are two outputs on the chip, one
being a low-skew divide by two of the other. So,
for instance, if an 81 MHz input clock is used, the
ICS543 can produce low skew 27 MHz and
13.5 MHz clocks. The chip has an all-chip power
down mode that stops the outputs low, and an OE
pin that tri-states the outputs.
The ICS543 is a member of the ICS
ClockBlocks family of clock building blocks.
See the ICS541 and ICS542 for other clock
dividers, and the ICS300, 501, 502, and 503 for
clock multipliers.
Block Diagram
Description
Features
Divider and
Selection
Circuitry
VDD GND
CLK
Output
Buffer
Output
Buffer
S1, S0
2
÷2
Input Clock
OE (both outputs)
CLK/2
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ICS544-01 | 制造商:ICS 制造商全稱:ICS 功能描述:Clock Divider |
| ICS544M-01 | 制造商:ICS 制造商全稱:ICS 功能描述:Clock Divider |
| ICS544M-01LF | 功能描述:IC CLK DIVIDER 16.777MHZ 8SOIC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:ClockBlocks™ 標準包裝:2,000 系列:- 類型:PLL 時鐘發生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數:1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| ICS544M-01LFT | 功能描述:IC CLK DIVIDER 16.777MHZ 8SOIC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:ClockBlocks™ 標準包裝:2,000 系列:- 類型:PLL 時鐘發生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數:1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| ICS544M-01T | 制造商:ICS 制造商全稱:ICS 功能描述:Clock Divider |
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