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參數(shù)資料
| 型號： | ICS620-01R |
| 英文描述： | Digital Still Camera Clock Source |
| 中文描述： | 數(shù)碼相機時鐘源 |
| 文件頁數(shù)： | 1/4頁 |
| 文件大小： | 64K |
| 代理商： | ICS620-01R |
The ICS620-01 is a low cost, low jitter, high
performance clock synthesizer for digital still
cameras. Using analog Phase-Locked Loop
(PLL) techniques, the device uses a
14.318 MHz crystal input to produce multiple
output clocks required in the camera. It
provides selectable NTSC/PAL clock, a
selectable processor clock, a selectable CCD
clock, and a selectable interface clocks. Most
clocks are generated to a very low ppm
synthesis error rate.
All clocks can be turned off using a power
down mode. Custom versions with user-
defined frequencies and power down modes
are available in 6-8 weeks.
Block Diagram
ICS620-01
Digital Still Camera Clock Source
MDS 620-01 B
Integrated Circuit Systems 1271
Parkmoor Ave.San JoseCA95126(408)295-9800tel(408)295-9818fax
1
Revision 072098 Printed 12/4/00
PRELIMINARY INFORMATION
ICRO
C
LOC K
Description
Features
Packaged in 28 pin, 150 mil wide SSOP (QSOP)
Provides all clocks necessary for many digital still
camera systems
All clocks are frequency locked together
Interface clock for USB, P1394, or UART
Saves space over multiple crystals and oscillators
Clocks power down when all select pins are low
Full CMOS outputs also compatible with TTL levels
+3.3 V or +5 V operation
Low power, sub-micron CMOS process
Custom versions available
Crystal
Oscillator
PLL Clock
Synthesis
Circuitry
CCD Clock 1
Processor Clock 1
2
NSEL1:0
14.31818
MHz
crystal
X1
X2
NTSC/PAL Clock 1
Interface Clock 2
Output
Buffer
Output
Buffer
PLL Clock
Synthesis
Circuitry
PLL Clock
Synthesis
Circuitry
PLL Clock
Synthesis
Circuitry
PSEL1:0
2
CSEL1:0
2
2
ISEL1:0
Output
Buffer
Output
Buffer
Interface Clock 1
CCD Clock 2
÷2
Output
Buffer
Output
Buffer
Output
Buffer
Output
Buffer
NTSC/PAL Clock 2
Processor Clock 2
÷2
÷2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS620-01RT | Digital Still Camera Clock Source |
| ICS627-01 | HDTV Set-Top Clock Source |
| ICS627R-01 | Inductor; Inductor Type:Power; Inductance:99.14uH; Inductance Tolerance:+/- 20 %; Series:CTX; Package/Case:ECONO-PAC; Core Material:Iron; DC Current, Parallel Full Load:0.62A; DC Current, Series Full Load:0.31A RoHS Compliant: Yes |
| ICS627R-01T | Inductor; Inductor Type:Power; Inductance:101.31uH; Inductance Tolerance:+/- 20 %; Series:CTX; Package/Case:ECONO-PAC; Core Material:Iron; DC Current, Parallel Full Load:0.68A; DC Current, Series Full Load:0.34A RoHS Compliant: Yes |
| ICS650-01B | System Peripheral Clock Source |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS620-01RT | 制造商:ICS 制造商全稱:ICS 功能描述:Digital Still Camera Clock Source |
| ICS620AK-06LF | 功能描述:IC CLOCK SYNTHESIZER PDA 32-QFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| ICS620AK-06LFT | 功能描述:IC CLOCK SYNTHESIZER PDA 32-QFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| ICS621 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:LOW SKEW 1 TO 4 CLOCK BUFFER |
| ICS62-1 | 制造商:Thomas & Betts 功能描述:INSULATED SERV.ENTR.SLEEVE 制造商:Thomas & Betts 功能描述:Cable Accessories Compression Splice Aluminum |
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