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參數資料
| 型號： | ICS810001DK-21LFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數： | 1/19頁 |
| 文件大小： | 0K |
| 描述： | IC CLK GEN SYNC VCXO DL 32VFQFN |
| 標準包裝： | 2,500 |
| 系列： | HiPerClockS™, FemtoClock™ |
| 類型： | 時鐘/頻率發生器，轉換器，抖動衰減器，多路復用器 |
| PLL： | 是 |
| 主要目的： | 視頻 |
| 輸入： | LVCMOS，LVTTL |
| 輸出： | LVCMOS，LVTTL |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 175MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 32-VFQFPN 裸露焊盤（4x4） |
| 包裝： | 帶卷 (TR) |
DATA SHEET
ICS810001DK-21 REVISION B APRIL 13, 2010
1
2010 Integrated Device Technology, Inc.
FemtoClock Dual VCXO Video PLL
ICS810001-21
General Description
The ICS810001-21 is a PLL based synchronous clock
generator that is optimized for digital video clock jitter
attenuation and frequency translation. The device
contains two internal frequency multiplication stages
that are cascaded in series. The first stage is a VCXO
PLL that is optimized to provide reference clock jitter attenuation,
and to support the complex PLL multiplication ratios needed for
video rate conversion. The second stage is a FemtoClock
frequency multiplier that provides the low jitter, high frequency video
output clock.
Preset multiplication ratios are selected from internal lookup tables
using device input selection pins. The multiplication ratios are
optimized to support most common video rates used in professional
video system applications. The VCXO requires the use of an
external, inexpensive pullable crystal. Two crystal connections are
provided (pin selectable) so that both 60 and 59.94 base frame rates
can be supported. The VCXO requires external passive loop filter
components which are used to set the PLL loop bandwidth and
damping characteristics.
Features
Jitter attenuation and frequency translation of video clock signals
Supports SMPTE 292M, ITU-R Rec. 601/656 and
MPEG-transport clocks
Support of High-Definition (HD) and Standard-Definition (SD)
pixel rates
Dual VCXO-PLL supports both 60 and 59.94Hz base frame rates
in one device
Supports both 1000/1001 and 1001/1000 rate conversions
Dual PLL mode for high-frequency clock generation (36MHz to
148.5MHz)
VCXO-PLL mode for low-frequency clock generation (27MHz and
26.973MHz)
One LVCMOS/LVTTL clock output
Two selectable LVCMOS/LVTTL clock inputs
LVCMOS/LVTTL compatible control signals
RMS phase jitter @148.3516MHz, (12kHz - 20MHz):
1.089ps (typical)
3.3V supply voltage
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Supported Input Frequencies
Supported Output Frequencies
HiPerClockS
ICS
fVCXO = 27MHz
fVCXO = 26.973MHz
27.0000MHz
26.9730MHz
27.0270MHz
27.0000MHz
74.1758MHz
74.1016MHz
74.3243MHz
74.2499MHz
74.2500MHz
74.1758MHz
27.0270MHz
27.0000MHz
26.9730MHz
26.9461MHz
74.1758MHz
74.1016kHz
45.0000kHz
44.9550kHz
33.7500kHz
33.7163kHz
15.6250kHz
15.6094kHz
15.7343kHz
15.7185kHz
28.1250kHz
28.0969kHz
fVCXO = 27MHz
fVCXO = 26.973MHz
148.5000MHz
148.3515MHz
74.2500MHz
74.1758MHz
49.5000MHz
49.4505MHz
33.0000MHz
32.9670MHz
162.0000MHz
161.8380MHz
81.0000MHz
80.9190MHz
54.0000MHz
53.9460MHz
36.0000MHz
35.9640MHz
27.0000MHz
26.9730MHz
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