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參數(shù)資料
| 型號(hào)： | ICS813001I |
| 英文描述： | DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK-TM PLL |
| 中文描述： | 雙壓控W/3.3V，2.5伏的LVPECL FEMTOCLOCK，商標(biāo)鎖相環(huán) |
| 文件頁數(shù)： | 1/18頁 |
| 文件大小： | 237K |
| 代理商： | ICS813001I |
813001AGI
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 2, 2005
1
Integrated
Circuit
Systems, Inc.
ICS813001I
D
UAL
VCXO
W
/3.3V, 2.5V LVPECL
F
EMTO
C
LOCK
PLL
G
ENERAL
D
ESCRIPTION
The ICS813001I is a dual VCXO + FemtoClock
Multiplier designed for use in Discrete PLL
loops. Two selectable external VCXO crystals
allow the device to be used in multi-rate appli-
cations, where a given line card can be
switched, for example, between 1Gb Ethernet (125MHz
system reference clock) and 1Gb Fibre Channel
(106.25MHz system reference clock) modes. Of course,
a multitude of other applications are also possible such
as switching between 74.25MHz and 74.175824MHz
for HDTV, switching between SONET, FEC and non FEC
rates, etc.
The ICS813001I is a two stage device – a VCXO followed
by a FemtoClock PLL. The FemtoClock PLL can multiply
the crystal frequency of the VCXO to provide an output
frequency range of 40.83MHz to 640MHz, with a random
rms phase jitter of less than 1ps (12kHz – 20MHz). This
phase jitter performance meets the requirements of 1Gb/
10Gb Ethernet, 1Gb, 2Gb, 4Gb and 10Gb Fibre Channel,
and SONET up to OC48. The FemtoClock PLL can also be
bypassed if frequency multiplication is not required. For
testing/debug purposes, de-assertion of the output enable
pin will place both Q and nQ in a high impedance state.
B
LOCK
D
IAGRAM
Pullup
F
EATURES
One 3.3V or 2.5V LVPECL output pair
Two selectable crystal oscillator interfaces for the VCXO,
one differential clock or one LVCMOS/LVTTL clock inputs
CLK1/nCLK1 supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
Crystal operating frequency range: 14MHz - 24MHz
VCO range: 490MHz - 640MHz
Output frequency range: 40.83MHz - 640MHz
VCXO pull range: ±100ppm (typical)
Supports the following applications (among others):
SONET, Ethernet, Fibre Channel, HDTV, MPEG
RMS phase jitter @ 622.08MHz (12kHz - 20MHz):
0.84 (typical)
Supply voltage modes:
V
/V
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
-40°C to 85°C ambient operating temperature
Available in both, Standard and RoHS/Lead-Free
compliant packages
HiPerClockS
ICS
VCXO
1 0
(default)
1 1
0 0
0 1
PD
VCO
490-640MHz
0
1
Feedback Divider M
M2:M0
000 ÷16
001 ÷20
010 ÷22
011 ÷24
100 ÷25
(default)
101 ÷32
110 ÷40
111 MR
Output Divider N
N2:N0
000 ÷1
001 ÷2
010 ÷3
011 ÷4
(default)
100 ÷5
101 ÷6
110 ÷8
111 ÷12
P
IN
A
SSIGNMENT
VCO_SEL
N0
N1
N2
V
CCO
Q
nQ
V
EE
V
CCA
V
CC
XTAL_OUT1
XTAL_IN1
12
ICS813001I
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
1
2
3
4
5
6
7
8
9
10
11
CLK_SEL1
CLK_SEL0
OE
M2
M1
M0
CLK1
nCLK1
CLK0
VC
XTAL_IN0
XTAL_OUT0
24
23
22
21
20
19
18
17
16
15
14
13
VCO_SEL
CLK_SEL0
CLK_SEL1
CLK0
CLK1
nCLK1
VC
M2
M1
M0
N2
N1
N0
OE
Pullup
Pullup
Q
nQ
XTAL_IN0
XTAL_OUT0
XTAL_IN1
XTAL_OUT1
Pulldown
Pulldown
Pullup
Pullup
Pullup
Pullup
Pulldown
Pulldown
Pulldown
Pulldown
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