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參數(shù)資料
| 型號： | ICS8344BY-01 |
| 英文描述： | Buffer/Driver |
| 中文描述： | 緩沖器/驅(qū)動器 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大小： | 120K |
| 代理商： | ICS8344BY-01 |
8344-01
www.icst.com
REV. A JANUARY 30, 2001
1
ICS8344-01
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS8344-01 is a low voltage, low skew
fanout buffer and a member of the HiPerClockS
family of High Performance Clock Solutions from
ICS. The ICS8344-01 is designed to translate any
differential signal levels to LVCMOS levels. The
low impedance LVCMOS outputs are designed to drive 50
series or parallel terminated transmission lines. The effective
fanout can be increased to 48 by utilizing the ability of the
outputs to drive two series terminated lines. Redundant clock
applications can make use of the dual clock input. The dual
clock inputs also facilitate board level testing. The output
enable is synchronous which eliminates the runt clock pulses
which occur during asynchronous enabling and disabling of
the outputs. The outputs are driven low when disabled. The
ICS8344-01 is characterized at full 3.3V, full 2.5V and mixed
3.3V input and 2.5V output operating supply modes.
Guaranteed output and part-to-part skew characteristics
make the ICS8344-01 ideal for those clock distribution
applications demanding well defined performance and
repeatability.
F
EATURES
24 LVCMOS outputs, 7
typical output impedance
Output frequency up to 250MHz
85ps bank skew, 200ps output skew, 900ps part to part
skew
Translates any differential input signal (PECL, HSTL, LVDS)
to LVCMOS without external bias networks
Translates any single ended input signal to LVCMOS with
resistor bias on nCLK input
Translates any single ended input signal to inverted
LVCMOS with resistor bias on CLK input
LVCMOS control inputs
Synchronous clock enable
3.3V, 2.5V or mixed 3.3V, 2.5V operating supply modes
48 lead low-profile QFP (LQFP), 7mm x 7mm x 1.4mm
package body, 0.5mm package lead pitch
0°C to 70°C ambient operating temperature
Industrial temperature version available upon request
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
HiPerClockS
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
Q16
Q17
VDDO
GND
Q18
Q19
Q20
Q21
VDDO
GND
Q22
Q23
Q7
Q6
VDDO
GND
Q5
Q4
Q3
Q2
VDDO
GND
Q1
Q0
n
O
C
C
n
V
G
C
n
V
G
C
Q
Q
V
G
Q
Q
Q
Q
V
G
Q
Q
48-Lead LQFP
Y Package
Top View
ICS8344-01
Q0 - Q7
O8 - Q15
O16 - Q23
CLK_SEL
CLK0
nCLK0
CLK1
nCLK1
CLK_EN
OE
0
1
LE
Q
nD
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS8344BY-01T | Buffer/Driver |
| ICS83840AH | DDR SDRAM MUX |
| ICS83840AHT | DDR SDRAM MUX |
| ICS83840 | Replaced by SN65MLVD205A : Full-Duplex M-LVDS Transceiver 14-SOIC -40 to 85 |
| ICS83840AHLF | DDR SDRAM MUX |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS8344BY-01T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Buffer/Driver |
| ICS8344BYI | 制造商:ICS 制造商全稱:ICS 功能描述:LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER |
| ICS8344BYILF | 功能描述:IC CLOCK BUFFER MUX 2:24 48-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:管件 |
| ICS8344BYILFT | 功能描述:IC CLOCK BUFFER MUX 2:24 48-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:管件 |
| ICS8344BYI-T | 制造商:ICS 制造商全稱:ICS 功能描述:LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER |
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