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參數資料
| 型號： | ICS8344I-01 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | LOW SKEW, 1-TO-24 DIFFERENTIAL -TO-LVCMOS/LVTTL FANOUT BUFFER |
| 中文描述： | 低偏移，1至24微分-TO-LVCMOS/LVTTL扇出緩沖器 |
| 文件頁數： | 1/13頁 |
| 文件大小： | 240K |
| 代理商： | ICS8344I-01 |
LOW SKEW, 1-TO-24 DIFFERENTIAL-
TO-LVCMOS/LVTTL FANOUT BUFFER
G
ENERAL
D
ESCRIPTION
The ICS8344I-01 is a low voltage, low skew
fanout buffer and a member of the HiPerClockS
family of High Performance Clock Solutions from
IDT. The ICS8344I-01 has two selectable clock in-
puts. The CLKx, nCLKx pairs can accept most
standard differential input levels. The ICS8344I-01 is designed
to translate any differential signal level to LVCMOS/LVTTL lev-
els. The low impedance LVCMOS/LVTTL outputs are designed
to drive 50
Ω
series or parallel terminated transmission lines.
The effective fanout can be increased to 48 by utilizing the
ability of the outputs to drive two series terminated lines.
Redundant clock applications can make use of the dual clock
inputs which also facilitate board level testing. The clock
enable is internally synchronized to eliminate runt pulses on
the outputs during asynchronous assertion/deassertion of the
clock enable pin. The outputs are driven low when disabled.
The ICS8344I-01 is characterized at full 3.3V, full 2.5V and
mixed 3.3V input and 2.5V output operating supply modes.
ICS 8344I-01
IDT
/ ICS
LVCMOS/LVTTL FANOUT BUFFER
1
ICS8344AYI-01 REV. B MAY 10, 2007
PRELIMINARY
Guaranteed output and part-to-part skew characteristics make
the ICS8344I-01 ideal for those clock distribution applications
demanding well defined performance and repeatability.
F
EATURES
Twenty-four LVCMOS/LVTTL outputs,
7
Ω
typical output impedance
Two selectable differential CLKx, nCLKx inputs
CLK0, nCLK0 and CLK1, nCLK1 pairs can accept the
following input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
Maximum
output
frequency
:
200
MHz
Translates any single ended input signal to LVCMOS/LVTTL
with resistor bias on nCLK input
Synchronous clock enable
Output skew: 250ps (maximum)
Part-to-part skew: 1ns (maximum)
Bank skew: 125ps (maximum)
Propagation delay: 5.25ns (maximum)
Output supply modes:
Core/Output
3.3V/3.3V
2.5V/2.5V
3.3V/2.5V
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
P
IN
A
SSIGNMENT
B
LOCK
D
IAGRAM
HiPerClockS
ICS
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
Q16
Q17
V
DDO
GND
Q18
Q19
Q20
Q21
V
DDO
GND
Q22
Q23
Q7
Q6
V
DDO
GND
Q5
Q4
Q3
Q2
V
DDO
GND
Q1
Q0
n
O
C
C
n
V
D
G
C
n
V
D
G
C
Q
Q
V
D
G
Q
Q
Q
Q
V
D
G
Q
Q
48-Lead LQFP
7mm x 7mm x 1.4mm
package body
Y Package
Top View
ICS8344-01
Q0:Q7
Q8:Q15
Q16:Q23
CLK_SEL
CLK0
nCLK0
CLK1
nCLK1
CLK_EN
OE
LE
Q
nD
0
1
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
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