
843001AGI-23
www.icst.com/products/hiperclocks.html
REV. B JANUARY 6, 2006
1
Integrated
Circuit
Systems, Inc.
ICS843001I-23
F
EMTO
C
LOCKS
C
RYSTAL
-
TO
-3.3V LVPECL/LVCMOS
F
REQUENCY
S
YNTHESIZER
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS843001I-23 is a highly versatile, low
phase noise LVPECL/LVCMOS Synthesizer
which can generate low jitter reference clocks
for a variety of communication applications
and is a member of the HiPerClocks
TM
family
of high performance clock solutions from ICS.
The dual crystal interface allows the synthesizer to
support up to three communication standards in a given
application (i.e. SONET with a 19.44MHz crystal, 1Gb/10Gb
Ethernet and Fibre Channel using a 25MHz crystal). The
rms phase jitter performance is typically less than 1ps, thus
making the device acceptable for use in demanding
applications such as OC48 SONET, GbE/10Gb Ethernet
and SAN applications. The ICS843001I-23 is packaged in
a small 24-pin TSSOP package.
F
EATURES
One 3.3V LVPECL output pair and
one LVCMOS/LVTTL REF_OUT output
Selectable crystal oscillator interfaces
or LVCMOS/LVTTL single-ended input
Crystal and CLK range: 17.5MHz - 29.54MHz
Able to generate GbE/10GbE/12GbE, Fibre Channel
(1Gb/4Gb/10Gb), PCI-E and SATA from a 25MHz crystal
VCO range: 1.12GHz - 1.3GHz
Supports the following applications:
SONET, Ethernet, Fibre Channel, Serial ATA, and HDTV
RMS phase jitter @ 622.08MHz (12kHz - 20MHz):
<1ps (typical) design target
Supply modes:
V
/V
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
-40°C to 85°C ambient operating temperature
Available in both standard and lead-free RoHS-compliant
packages
HiPerClockS
ICS
P
IN
A
SSIGNMENT
11
10
01
00
00
01
10
11
Phase
Detector
VCO
000 ÷44
001 ÷45
010 ÷48
011 ÷50
100 ÷51
111 ÷64
(default)
N
000 ÷2
001 ÷4
010 ÷5
011 ÷6
100 ÷8
(default)
101 ÷10
110 ÷12
111 ÷16
M
3
3
OSC
OSC
ICS843001I-23
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
V
CCO
_
LVCMOS
N0
N1
N2
V
CCO
_
LVPECL
Q
nQ
V
EE
V
CCA
V
CC
XTAL_OUT1
XTAL_IN1
1
2
3
4
5
6
7
8
9
10
11
12
REF_OUT
V
EE
OE_REF
M2
M1
M0
MR
SEL1
SEL0
CLK
XTAL_IN0
XTAL_OUT0
24
23
22
21
20
19
18
17
16
15
14
13
B
LOCK
D
IAGRAM
N2:N0
SEL0
SEL1
XTAL_IN0
XTAL_OUT0
XTAL_IN1
XTAL_OUT1
CLK
MR
M2:M0
OE_REF
Q
nQ
Pulldown
Pulldown
Pulldown
Pulldown
REF_OUT
Pulldown
Pullup
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.