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參數資料
型號: ICS9248YG-50-T
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產生/分配
英文描述: 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28
封裝: 6.10 MM, 0.65 MM PITCH, TSSOP-28
文件頁數: 1/11頁
文件大小: 261K
代理商: ICS9248YG-50-T
Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9248-50
Block Diagram
Frequency Timing Generator for Pentium II Systems
9248-50 Rev - H 03/19/01
Pin Configuration
Pentium is a trademark on Intel Corporation.
Generates the following system clocks:
- 2 CPU (2.5V) up to 100MHz.
- 6 PCI (3.3V) @ 33.3MHz (Includes one free running).
- 2 REF clks (3.3V) at 14.318MHz.
Skew characteristics:
- CPU – CPU<175ps
- PCI – PCI < 500ps
- CPU(early) – PCI = 1.5ns – 4ns.
Supports Spread Spectrum modulation for CPU and PCI
clocks, 0.5% down spread
Efficient Power management scheme through stop
clocks and power down modes.
Uses external 14.318MHz crystal, no external load cap
required for CL=18pF crystal.
28-pin (209 mil) SSOP and (6.1mm) TSSOP package
The ICS9248-50 is the Main clock solution for Notebook
designs using the Intel 440BX style chipset. Along with an
SDRAM buffer such as the ICS9179-03, it provides all
necessary clock signals for such a system.
Spread spectrum may be enabled by driving pin 26, SPREAD#
active (Low) at power-on. Spread spectrum typically reduces
system EMI by 8dB to 10dB. This simplifies EMI qualification
without resorting to board design iterations or costly shielding.
The ICS9248-50 employs a proprietary closed loop design,
which tightly controls the percentage of spreading over
process and temperature variations.
Power Groups
VDD, GND = PLL core
VDDREF, GNDREF = REF(0:1), X1, X2
VDDPCI, GNDPCI = PCICLK_F, PCICLK (0:4)
VDD48, GND48 = 48MHz, 48/24MHz
28-Pin SSOP & TSSOP
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
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