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參數資料
| 型號： | ICS9248YG-50T |
| 英文描述： | Peripheral IC |
| 中文描述： | 外圍芯片 |
| 文件頁數： | 1/12頁 |
| 文件大小： | 471K |
| 代理商： | ICS9248YG-50T |
ICS9248-126
Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
Block Diagram
9248-126 Rev C 9/6/00
Recommended Application:
!"
Output Features:
3- CPUs @ 2.5/3.3V, up to 166MHz.
14 - SDRAM @ 3.3V
7- PCI @3.3V,
1- 48MHz, @3.3V fixed.
1- 24/48MHz, @3.3V selectable by I
2
C
(Default is 24MHz).
2- REF @3.3V, 14.318MHz.
Features:
Up to 166MHz frequency support
Support FS0-FS3 trapping status bit for I
2
C read back.
Support power management: CPU, PCI, SDRAM stop
and Power down Mode form I
2
C programming.
Spread spectrum for EMI control (0 to -0.5%, ± 0.25%).
FS0, FS1, FS3 must have a internal 120K pull-Down
to GND.
Uses external 14.318MHz crystal
Skew Specifications:
CPU - CPU: < 175ps
SDRAM - SDRAM < 500ps
PCI - PCI: < 500ps
CPU - SDRAM: < 500ps
CPU - PCI: 1 - 4ns
Functionality
CPU2.5_3.3#
PLL2
PLL1
Spread
Spectrum
48MHz
24_48MHz
CPUCLK (2:0)
SDRAM (13:0)
PCICLK (6:0)
X1
X2
XTAL
OSC
PCI
CLOCK
DIVDER
CPU
CLOCK
DIVDER
SDRAM
CLOCK
DIVDER
SDATA
SCLK
FS(3:0)
Control
Logic
Config.
Reg.
/ 2
REF (1:0)
LATCH
2
3
14
7
4
Pin Configuration
48-Pin 300mil SSOP
#$%&'()*+"
&
$ "
Frequency Generator & Integrated Buffers for Celeron & P
II
/
III
& K6
VDDREF
* REF0/FS3
GND
X1
X2
VDDPCI
*PCICLK0/FS1
*PCICLK1/FS2
PCICLK2
GND
PCICLK3
PCICLK4
PCICLK5
PCICLK6
VDDSDR
GND
SDRAM0
SDRAM1
VDDSDR
SDRAM2
SDRAM3
GND
SDATA
SCLK
REF1
VDDLCPU
CPUCLK0
CPUCLK1
GND
CPUCLK2
VDDSDR
SDRAM13
SDRAM12
GND
SDRAM11
SDRAM10
VDDSDR
SDRAM9
SDRAM8
GNDSDR
SDRAM7
SDRAM6
VDDSDR
SDRAM5
SDRAM4
VDDSDR
48MHz/FS0*
24_48MHz/CPU2.5_3.3#*
1
I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
3
S
F
2
S
F
1
S
F
0
S
F
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)
H
6
6
0
0
1
0
5
1
3
3
1
8
6
0
0
1
0
0
1
3
3
1
8
6
0
9
0
7
0
9
0
9
0
1
1
0
9
2
9
P
C
M
(
M
A
)
H
0
0
0
0
0
0
0
0
6
3
1
3
3
1
0
5
1
3
3
1
8
6
0
9
0
0
1
0
9
7
2
1
0
1
1
3
2
1
2
9
R
D
M
(
1
1
1
1
S
K
L
)
C
H
3
3
3
3
5
3
3
3
4
3
3
3
5
3
3
3
4
3
3
3
0
3
7
3
7
3
3
3
2
3
1
3
I
C
M
(
P
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ICS9248YG-50-T | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Timing Generator for Pentium II Systems |
| ICS9248YG-56-T | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Timing Generator for Pentium II Systems |
| ICS9248YG-92 | 制造商:ICS 制造商全稱:ICS 功能描述:Mobile Pentium IITM System Clock Chip |
| ICS9250-08 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| ICS9250-09 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Timing Generator for PENTIUM II Systems |
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