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參數資料
| 型號： | ICS950227 |
| 英文描述： | Programmable Timing Control Hub for P4 |
| 中文描述： | 可編程定時控制中心，為小 |
| 文件頁數： | 1/17頁 |
| 文件大小： | 128K |
| 代理商： | ICS950227 |
Integrated
Circuit
Systems, Inc.
ICS950227
0641D—07/03/03
Block Diagram
Pin Configuration
56-Pin 300-mil SSOP
Frequency Table
Recommended Application:
CK-408 clock Intel 845 with P4 processor.
Output Features:
3 Differential CPU Clock Pairs @ 3.3V
7 PCI (3.3V) @ 33.3MHz
3 PCI_F (3.3V) @ 33.3MHz
1 USB (3.3V) @ 48MHz
1 DOT (3.3V) @ 48MHz
1 REF (3.3V) @ 14.318MHz
5 3V66 (3.3V) @ 66.6MHz
1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
Features/Benefits:
Programmable output frequency.
Programmable output divider ratios.
Programmable output rise/fall time.
Programmable output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system
if system malfunctions.
Programmable watch dog safe frequency.
Support I
2
C Index read/write and block read/write
operations.
Uses external 14.318MHz crystal.
Key Specifications:
CPU Output Jitter <150ps
3V66 Output Jitter <250ps
CPU Output Skew <100ps
* These inputs have 150K internal pull-up resistor to VDD.
Programmable Timing Control Hub for P4
2
S
F
1
S
F
0
S
F
U
)
P
H
C
M
(
6
6
)
H
V
3
M
(
]
u
]
6
)
H
M
6
6
6
6
6
6
6
6
6
e
K
L
C
T
v
s
e
R
v
s
e
R
B
V
(
6
3
6
F
I
)
H
3
3
3
3
3
3
3
3
e
L
C
T
v
s
e
R
v
s
e
R
_
C
C
P
M
P
(
0
0
0
0
d
M
d
M
d
M
d
M
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
6
6
6
0
0
1
0
0
2
3
3
1
e
L
C
T
v
s
e
R
v
s
e
R
6
6
6
6
6
6
6
6
6
6
6
6
e
L
C
T
v
s
e
R
v
s
e
R
3
3
3
3
0
0
3
6
6
6
2
K
4
K
4
e
e
8
K
d
d
e
e
d
d
e
e
d
d
d
d
e
e
VDDREF
1
2
3
4
5
6
7
8
9
56 REF
55 FS1
54 FS0
53 CPU_STOP#*
52 CPUCLKT0
51 CPUCLKC0
50 VDDCPU
49 CPUCLKT1
48 CPUCLKC1
47 GND
46 VDDCPU
45 CPUCLKT2
44 CPUCLKC2
43 MULTSEL0*
42 IREF
41 GND
40 FS2
39 48MHz_USB
38 48MHz_DOT
37 VDD48
36 GND
35 3V66_1/VCH_CLK
34 PCI_STOP#*
33 3V66_0
32 VDD3V66
31 GND
30 SCLK
29 SDATA
X1
X2
GND
PCICLK_F0
PCICLK_F1
PCICLK_F2
VDDPCI
GND
PCICLK0 10
PCICLK1 11
PCICLK2 12
PCICLK3 13
VDDPCI 14
GND 15
PCICLK4 16
PCICLK5 17
PCICLK6 18
VDD3V66 19
GND 20
3V66_2 21
3V66_3 22
3V66_4 23
3V66_5 24
*PD# 25
VDDA 26
GND 27
Vtt_PWRGD# 28
I
PLL2
PLL1
Spread
Spectrum
48MHz_USB
PCICLK (6:0)
3V66 (5:2,0)
48MHz_DOT
3V66_1/VCH_CLK
X1
WDEN
PD#
XTAL
OSC
CPU
DIVDER
PCI
DIVDER
D3V66
CPU_STOP#
PCI_STOP#
MULTSEL0
FS (2:0)
SDATA
SCLK
Vtt_PWRGD#
I REF
Control
Logic
Config.
Reg.
REF
3
3
7
5
3
CPUCLKT (2:0)
CPUCLKC (2:0)
PCICLK_F (2:0)
Stop
Stop
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