- 您現在的位置：買賣IC網 > PDF目錄360785 > ICS950602yGT Programmable Timing Control Hub for PII/III PDF資料下載
參數資料
| 型號： | ICS950602yGT |
| 英文描述： | Programmable Timing Control Hub for PII/III |
| 中文描述： | 可編程定時控制中心，為PII /三 |
| 文件頁數： | 1/16頁 |
| 文件大小： | 147K |
| 代理商： | ICS950602YGT |
Integrated
Circuit
Systems, Inc.
ICS950602
0469B—12/18/02
Block Diagram
Pin Configuration
Recommended Application:
VIA Mobile PL133T and PLE133T Chipsets.
Output Features:
2 - CPU clocks @ 2.5V
1 - Pairs of differential CPU clocks @ 3.3V
7 - PCI including 1 free running @ 3.3V
7 - SDRAM @ 3.3V
1 - 48MHz @ 3.3V fixed
1 - 24_48MHz selectable @ 3.3V
2 - REF @ 3.3V, 14.318MHz
Features/Benefits:
Programmable output frequency.
Programmable output divider ratios.
Programmable output rise/fall time.
Programmable output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system
if system malfunctions.
Programmable watch dog safe frequency.
Support I
2
C Index read/write and block read/write
operations.
Uses external 14.318MHz crystal.
Key Specifications:
CPU Output Jitter <200ps
CPU Output Skew <175ps
PCI to PCI Output Skew <500ps
Programmable Timing Control Hub for P
II
/
III
* Internal Pull-up resistor of 120K to VDD
** these inputs have 120K internal pull-down
to GND
48-Pin SSOP & TSSOP
GND
VDDREF
X2
VDDPCI
*FS3/PCICLK0
GND
*PCI_STOP#
*PD#
**MULTISEL
SDATA
SCLK
*FS2/REF1
REF0
Vtt_PWRGD#
GND
X1
*FS4/PCICLK_F
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
SDRAM_IN
*CPU_STOP#
GND
CPUCLK0
CPUCLK1
VDDCPU_2.5
VDDCPU_3.3
CPUCLKT
CPUCLKC
GND
RESET#
I REF
SDRAM6
GND
SDRAM0
SDRAM1
VDDSDRAM
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDSDRAM
AVDD48
48MHz/FS0*
24_48MHz/FS1*
I
9
24
25
1
2
3
4
5
6
7
8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
Host Swing Select Functions
0
L
E
S
I
L
U
M
t
Z
g
T
r
d
o
T
c
a
B
m
,
)
R
R
*
e
c
3
n
e
R
=
f
V
D
D
t
t
p
O
e
C
Z
@
h
o
V
0
s
m
h
o
0
5
,
%
m
1
1
2
2
0
=
=
r
R
f
A
0
F
E
R
I
*
4
=
h
o
0
5
@
V
0
1
s
m
h
o
0
5
,
%
m
1
5
7
4
3
=
=
r
R
f
A
2
F
E
R
I
*
6
=
h
o
0
5
@
V
7
相關PDF資料 |
PDF描述 |
|---|---|
| ICS950602yFT | POT 25K OHM 1/4 SQ CERM SL ST |
| ICS950805G-T | Frequency Generator with 200MHz Differential CPU Clocks |
| ICS950805 | 16-Bit Buffers/Drivers With 3-State Outputs 48-SSOP -40 to 85 |
| ICS950805F-T | Frequency Generator with 200MHz Differential CPU Clocks |
| ICS950810 | Frequency Generator with 200MHz Differential CPU Clocks |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ICS950703 | 制造商:ICS 制造商全稱:ICS 功能描述:PROGRAMMABLE TIMING CONTROL HUB FOR P4 |
| ICS950703XFLF-T | 制造商:ICS 制造商全稱:ICS 功能描述:PROGRAMMABLE TIMING CONTROL HUB FOR P4 |
| ICS950805 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator with 200MHz Differential CPU Clocks |
| ICS950805F-T | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator with 200MHz Differential CPU Clocks |
| ICS950805G-T | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator with 200MHz Differential CPU Clocks |
發布緊急采購，3分鐘左右您將得到回復。