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參數資料
| 型號： | ICS950812YGLFT |
| 英文描述： | Frequency Generator with 200MHz Differential CPU Clocks |
| 中文描述： | 頻率發生器200MHz的CPU的時鐘差分 |
| 文件頁數： | 1/29頁 |
| 文件大小： | 225K |
| 代理商： | ICS950812YGLFT |
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Integrated
Circuit
Systems, Inc.
ICS950812
0542G—08/21/03
Block Diagram
Recommended Application:
CK-408 clock with Buffered/Unbuffered mode supporting
Almador, Brookdale, ODEM, and Montara-G chipsets with
PIII/P4 processor. Programmable for group to group skew.
Output Features:
3 Differential CPU Clock Pairs @ 3.3V
7 PCI (3.3V) @ 33.3MHz including 2 early PCI clocks
3 PCI_F (3.3V) @ 33.3MHz
1 USB (3.3V) @ 48MHz, 1 DOT (3.3V) @ 48MHz
1 REF (3.3V) @ 14.318MHz
5 3V66 (3.3V) @ 66.6MHz
1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
3 66MHz_OUT/3V66 (3.3V) @ 66.6MHz_IN or 66.6MHz
Features:
Provides standard frequencies and additional 5%
and 10% over-clocked frequencies
Supports spread spectrum modulation:
No spread, Center Spread (±0.35%, ±0.5%,
or ±0.75%), or Down Spread (-0.5%, -1.0%, or -1.5%)
Offers adjustable PCI early clock via latch inputs
Selectable 1X or 2X strength for REF via I
2
C interface
Efficient power management scheme through PD#,
CPU_STOP# and PCI_STOP#.
Uses external 14.318MHz crystal
Stop clocks and functional control available through
I
2
C interface.
Key Specifications:
CPU Output Jitter <150ps
3V66 Output Jitter <250ps
66MHz Output Jitter (Additive) (Buffered Mode) <100ps
CPU Output Skew <100ps
Pin Configuration
Frequency Generator with 200MHz Differential CPU Clocks
Frequency Select
Note:
Almador board level designs MUST use pin 22,
66MHZ_OUT1, as the feedback connection from the
clock buffer path to the Almador (GMCH) chipset.
66MHz_OU
T (2:0)
3V66 (4:2)
MHz
66.66
66.66
66.66
66.66
66MHz_IN
66MHz_IN
66MHz_IN
66MHz_IN
66MHz_IN
PCICLK_F
3V66_5
MHz
66.66
66.66
66.66
66.66
Input
Input
Input
Input
PCICLK
MHz
33.33
33.33
33.33
33.33
66MHz_IN/2
66MHz_IN/2
66MHz_IN/2
66MHz_IN/2
FS2 FS1 FS0
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
MHz
66.66
100.00
200.00
133.33
66.66
100.00
200.00
133.33
MHz
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
0
1
0
1
0
1
0
1
CPUCLK
3V66
Bit
PLL2
PLL1
Spread
Spectrum
3V66_5/66MHz_IN
3V66_3/66MHz_OUT1
3V66_(4,2)/66MHz_OUT(2,0)
48MHz_USB
48MHz_DOT
X1
X2
XTAL
OSC
3V66
DIVDER
PD#
CPU_STOP#
PCI_STOP#
MULTSEL
FS (5:0)
SDATA
SCLK
I REF
Control
Logic
Config.
Reg.
REF
3V66_0
DCPU
3
3
CPUCLKT (2:0)
CPUCLKC (2:0)
Stop
3V66_1/VCH_CLK
PCICLK (6:4, 2, 0)
PCI
DIVDER
3
7
PCICLK_F (2:0)
Stop
E_PCICLK(1,3)/PCICLK(1,3)
2
V
TT
_PWRGD#
VDDREF
1
2
3
4
5
6
7
8
9
56 REF
55 FS1
54 FS0
53 CPU_STOP#*
52 CPUCLKT0
51CPUCLKC0
50 VDDCPU
49 CPUCLKT1
48 CPUCLKC1
47 GND
46 VDDCPU
45 CPUCLKT2
44 CPUCLKC2
43 MULTSEL*
42 IREF
41 GND
40 FS2
39 48MHz_USB/FS3
**
38 48MHz_DOT
37 VDD48
36 GND
35 3V66_1/VCH_CLK/FS4
**
34 PCI_STOP#*
33 3V66_0/FS5
**
32 VDD3V66
31 GND
30 SCLK
29 SDATA
X1
X2
GND
PCICLK_F0
PCICLK_F1
PCICLK_F2
VDDPCI
GND
PCICLK0 10
**E_PCICLK1/PCICLK1 11
PCICLK2 12
**E_PCICLK3/PCICLK3 13
VDDPCI 14
GND 15
PCICLK4 16
PCICLK5 17
PCICLK6 18
VDD3V66 19
GND 20
66MHZ_OUT0/3V66_2 21
66MHZ_OUT1/3V66_3 22
66MHZ_OUT2/3V66_4 23
66MHZ_IN/3V66_5 24
*PD# 25
VDDA 26
GND 27
Vtt_PWRGD# 28
56-Pin 300mil SSOP
6.10 mm. Body, 0.50 mm. pitch TSSOP
*
These inputs have 120K internal pull-up resistors to VDD.
**
Internal pull-down resistors to ground.
I
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