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參數(shù)資料
| 型號： | ICS950902YFLF-T |
| 英文描述： | Programmable Timing Control Hub⑩ for P4⑩ |
| 中文描述： | 可編程定時控制中心，為小四至⑩⑩ |
| 文件頁數(shù)： | 1/20頁 |
| 文件大小： | 184K |
| 代理商： | ICS950902YFLF-T |
Integrated
Circuit
Systems, Inc.
ICS950902
0475G—03/23/04
Pin Configuration
Recommended Application:
VIA P4X/P4M/KT/KN266/333 style chipsets.
Output Features:
1 - Pair of differential CPU clocks @ 3.3V (CK408)/
1 - Pair of differential open drain CPU clocks (K7)
1 - Pair of differential push pull CPU_CS clocks @ 2.5V
3 - AGP @ 3.3V
7 - PCI @ 3.3V (1 - Free running)
1 - 48MHz @ 3.3V fixed
1 - 24_48MHz @ 3.3V (Default 48MHz I
2
C select only)
2 - REF @ 3.3V, 14.318MHz
12 - SDRAM (6 pair - DDR) selectable
Key Specifications:
CPU_CS - CPUT/C: <±250ps
CPU_CS - AGP: <±250ps
CPU - DDR/SD: <±250ps
PCI - PCI: <500ps
CPU - PCI: Min = 1.0ns, Typ = 2.0ns, Max = 4.0ns
Programmable Timing Control Hub for P4
* Internal 120K pull-up resistor to VDD.
** Internal 120K pull-down resistor to GND.
56-Pin 300-mil SSOP & 240-mil TSSOP
Frequency Table
0
L
E
S
I
L
U
M
t
Z
g
T
r
d
o
T
c
a
B
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R
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n
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R
f
3
V
D
D
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p
O
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C
Z
@
h
o
V
0
s
m
h
o
0
5
,
%
m
1
1
2
2
0
=
=
r
R
f
A
0
F
E
R
I
*
4
=
h
o
0
5
@
V
0
1
s
m
h
o
0
5
,
%
m
1
5
7
4
3
=
=
r
R
f
A
2
F
E
R
I
*
6
=
h
o
0
5
@
V
7
3
S
F
2
S
F
1
S
F
0
S
F
K
L
z
C
H
U
M
P
C
P
z
G
H
A
M
K
L
z
C
H
I
C
M
P
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
6
1
0
6
1
6
6
1
0
7
1
0
7
1
0
8
1
0
8
1
0
9
1
8
6
9
0
1
6
3
1
4
0
2
6
6
0
0
1
0
0
2
3
3
1
0
0
0
0
0
0
0
0
0
7
0
0
0
0
0
0
0
8
0
8
6
6
0
6
0
7
0
7
0
7
0
7
8
6
2
6
8
6
8
6
6
6
6
6
6
6
6
6
0
0
0
0
0
0
0
0
0
3
0
0
0
0
0
0
0
4
0
4
3
3
0
3
0
3
0
3
0
3
0
3
4
3
6
3
4
3
4
3
3
3
3
3
3
3
3
3
0
0
0
0
0
0
0
0
*FS0/REF0 1
GND 2
56 Vtt_PWRGD#**/REF1
55 VDDREF
54 GND
53 CPUCLKT/CPUCLKODT
52 CPUCLKC/CPUCLKODC
51 VDDCPU3.3
50 VDDCPU2.5
49 CPUC_CS
48 CPUT_CS
47 GND
46 FBOUT
45 BUF_IN
44 DDRT0/SDRAM0
43 DDRC0/SDRAM1
42 DDRT1/SDRAM2
41 DDRC1/SDRAM3
40 VDD3.3_2.5
39 GND
38 DDRT2/SDRAM4
37 DDRC2/SDRAM5
36 DDRT3/SDRAM6
35 DDRC3/SDRAM7
34 VDD3.3_2.5
33 GND
32 DDRT4/SDRAM8
31 DDRC4/SDRAM9
30 DDRT5/SDRAM10
29 DDRC5/SDRAM11
X1 3
X2 4
VDDAGP 5
*MODE/AGPCLK0 6
*SEL_408/K7/AGPCLK1 7
*(PCI_STOP#)AGPCLK2 8
GNDAGP 9
**FS1/PCICLK_F 10
**SEL_SDR/DDR#/PCICLK1 11
*MULTSEL/PCICLK2 12
GNDPCI 13
PCICLK3 14
PCICLK4 15
VDDPCI 16
PCICLK5 17
*(CLK_STOP#)PCICLK6 18
GND48 19
*FS3/48MHz 20
*FS2/24_48MHz 21
AVDD48 22
VDD 23
GND 24
IREF 25
*(PD#)RESET# 26
SCLK 27
SDATA 28
I
Features/Benefits:
Programmable output frequency.
Programmable output divider ratios.
Programmable output rise/fall time.
Programmable output skew.
Programmable spread percentage for EMI control.
DDR output buffer supports up to 200MHz.
Watchdog timer technology to reset system
if system malfunctions.
Programmable watch dog safe frequency.
Support I
2
C Index read/write and block read/write
operations.
Uses external 14.318MHz crystal.
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| ICS950908BFLF | 功能描述:IC TIMING CTRL HUB P4 56-SSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:TCH™ 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| ICS950908BFLFT | 功能描述:IC TIMING CTRL HUB P4 56-SSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:TCH™ 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
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