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參數資料
| 型號： | ICS952001YGT |
| 元件分類： | 時鐘產生/分配 |
| 英文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | TSSOP-48 |
| 文件頁數： | 1/17頁 |
| 文件大小： | 212K |
| 代理商： | ICS952001YGT |
Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
Block Diagram
952001 Rev A 01/24/02
Pin Configuration
Recommended Application:
SIS 645/650 style chipsets.
Output Features:
2 - Pairs of differential CPUCLKs (differential current mode)
1 - SDRAM @ 3.3V
8 - PCI @3.3V
2 - AGP @ 3.3V
2 - ZCLKs @ 3.3V
1- 48MHz, @3.3V fixed.
1- 24/48MHz, @3.3V selectable by I
2C
(Default is 24MHz)
3- REF @3.3V, 14.318MHz.
Features/Benefits:
Programmable output frequency, divider ratios, output
rise/falltime, output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system
if system malfunctions.
Programmable watch dog safe frequency.
Support I
2C Index read/write and block read/write
operations.
For PC133 SDRAM system use the ICS9179-06 as the
memory buffer.
For DDR SDRAM system use the ICS93705 or
ICS93722 as the memory buffer.
Uses external 14.318MHz crystal.
Key Specifications:
PCI - PCI output skew: < 500ps
CPU - SDRAM output skew: < 1ns
AGP - AGP output skew: <150ps
Programmable Timing Control Hub for P4 processor
* These inputs have a 120K pull up to VDD.
** These inputs have a 120K pull down to GND.
48-Pin 300-mil SSOP and TSSOP
Functionality
Power Groups
VDDCPU = CPU
VDDPCI = PCICLK_F, PCICLK
VDDSD = SDRAM
AVDD48 = 48MHz, 24MHz, fixed PLL
AVDD = Analog Core PLL
VDDAGP= AGP
VDDREF = Xtal, REF
VDDZ = ZCLK
Note: For additional margin testing frequencies, refer to Byte 4
VDDREF
FS0/REF0
*FS1/REF1
X1
X2
GNDZ
ZCLK0
VDDPCI
PCICLK0
PCICLK1
GNDPCI
VDDPCI
**
*
**FS2/REF2
GNDREF
ZCLK1
VDDZ
*PCI_STOP#
**FS3/PCICLK_F0
**FS4/PCICLK_F1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
GNDPCI
VDDSD
SDRAM
GNDSD
CPU_STOP#
PD#*/Vtt_PWRGD
GNDAGP
AGPCLK0
AGPCLK1
VDDAGP
VDDA48
48MHz
24_48MHz/MULTISEL
GND48
*
CPUCLKT_1
CPUCLKC_1
VDDCPU
GNDCPU
CPUCLKT_0
CPUCLKC_0
IREF
GNDA
VDDA
SCLK
SDATA
*
ICS952001
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
I REF
CPU
DIVDER
PLL2
PLL1
Spread
Spectrum
48MHz
24_48MHz
ZCLK (1:0)
PCICLK (9:0)
AGP (1:0)
PCICLK_F (1:0)
2
6
2
X1
X2
XTAL
OSC
ZCLK
DIVDER
PCI
DIVDER
Stop
SDATA
SCLK
FS (4:0)
PD#
PCI_STOP#
CPU_STOP#
MULTISEL
PD#/Vtt_PWRGD
Control
Logic
Config.
Reg.
/ 2
REF (1:0)
AGP
DIVDER
Stop
2
CPUCLKT (1:0)
CPUCLKC (1:0)
B i t 2 B it 7 B it 6 B it 5 B it 4
C P U
S D R A M
Z C L K
A G P
FS 4
FS 3
FS 2
FS 1
FS 0
(M H z )
0
66. 67
6 6 . 6 7
0
1
100. 00
66. 67
6 6 . 6 7
0
1
0
100. 00
200. 00
66. 67
6 6 . 6 7
0
1
100. 00
133. 33
66. 67
6 6 . 6 7
0
1
0
100. 00
150. 00
60. 00
6 0 . 0 0
0
1
0
1
100. 00
125. 00
62. 50
6 2 . 5 0
0
1
0
100. 00
160. 00
66. 67
6 6 . 6 7
0
1
100. 00
133. 33
80. 00
6 6 . 6 7
0
1
0
100. 00
200. 00
66. 67
6 6 . 6 7
0
1
0
1
100. 00
166. 67
62. 50
6 2 . 5 0
0
1
0
1
0
100. 00
166. 67
71. 43
8 3 . 3 3
0
1
0
1
80. 00
133. 33
66. 67
6 6 . 6 7
0
1
0
80. 00
133. 33
66. 67
6 6 . 6 7
0
1
0
1
95. 00
63. 33
6 3 . 3 3
0
1
0
95. 00
126. 67
63. 33
6 3 . 3 3
0
111
1
66. 67
50. 00
5 0 . 0 0
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