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參數(shù)資料
| 型號(hào)： | ICS95V857YGLFT |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | 0.240 INCH, TSSOP-48 |
| 文件頁(yè)數(shù)： | 1/13頁(yè) |
| 文件大小： | 188K |
| 代理商： | ICS95V857YGLFT |
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Integrated
Circuit
Systems, Inc.
Preliminary Product Preview
ICS95V857-XXX
0674I—03/28/03
Block Diagram
2.5V Wide Range Frequency Clock Driver (33MHz - 233MHz)
Pin Configuration
48-Pin TSSOP/TVSOP
Recommended Application:
DDR Memory Modules / Zero Delay Board Fan Out
Product Description/Features:
Low skew, low jitter PLL clock driver
1 to 10 differential clock distribution (SSTL2)
Feedback pins for input to output synchronization
PD# for power management
Spread Spectrum-tolerant inputs
Auto PD when input signal removed
Choice of static phase offset available,
for easy board tuning;
-XXX = device pattern number for options listed
below.
- ICS95V857 ............. 0ps
- ICS95V857-130 .. +50ps
Specifications:
Meets or exceeds JEDEC standard #82-1 for
registered DDR clock driver.
Meets or exceeds proposed DDR1-400 specifications
Covers all DDR1 speed grades
Switching Characteristics:
CYCLE - CYCLE jitter (>100MHz):<50ps
OUTPUT - OUTPUT skew: <30ps
Output Rise and Fall Time: 650ps - 950ps
DUTY CYCLE: 49.5% - 50.5%
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Functionality
PLL
FB_INT
FB_INC
CLK_INC
CLK_INT
PD#
Control
Logic
FB_OUTT
FB_OUTC
CLKT0
CLKT1
CLKT2
CLKT3
CLKT4
CLKT5
CLKT6
CLKT7
CLKT8
CLKT9
CLKC0
CLKC1
CLKC2
CLKC3
CLKC4
CLKC5
CLKC6
CLKC7
CLKC8
CLKC9
6.10 mm Body, 0.50 mm Pitch = TSSOP
4.40 mm Body, 0.40 mm Pitch = TVSOP
GND
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
CLKC2
CLKT2
VDD
CLK_INT
CLK_INC
VDD
AVDD
AGND
GND
CLKC3
CLKT3
VDD
CLKT4
CLKC4
GND
CLKC5
CLKT5
VDD
CLKT6
CLKC6
GND
CLKC7
CLKT7
VDD
PD#
FB_INT
FB_INC
VDD
FB_OUTC
FB_OUTT
GND
CLKC8
CLKT8
VDD
CLKT9
CLKC9
GND
ICS95V857-XXX
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PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are
subject to change without notice.
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| ICS95V857YGT | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| ICS95V857YG-130LF | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| ICS95V857YHT | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA56 |
| ICS97U870YHLFT | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 |
| ICS97U870YKLFT | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC40 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS95V860 | 制造商:ICS 制造商全稱:ICS 功能描述:2.5V DDR/Zero Delay Fan Out Buffer (100MHz - 225MHz) |
| ICS95V860YHLF-T | 制造商:ICS 制造商全稱:ICS 功能描述:2.5V DDR/Zero Delay Fan Out Buffer (100MHz - 225MHz) |
| ICS95VLP857AGLF | 功能描述:IC CLOCK DRIVER 2.5V 48-TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無(wú)/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| ICS95VLP857AGLFT | 功能描述:IC CLOCK DRIVER 2.5V 48-TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無(wú)/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| ICS95VLP857AGLF-T | 制造商:INTEGRATED DEVICE TECHNOLOGY 功能描述: |
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