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參數資料
| 型號： | IDT54FCT646CTP |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | Ceramic Chip Capacitors / Standard X7R; Capacitance [nom]: 2.2uF; Working Voltage (Vdc)[max]: 50V; Capacitance Tolerance: +/-10%; Dielectric: Multilayer Ceramic; Temperature Coefficient: X7R; Lead Style: Surface Mount Chip; Lead Dimensions: 1210; Termination: Tin Plated Nickel Barrier; Body Dimensions: 0.126" x 0.098"; Container: Bulk; Features: Unmarked |
| 中文描述： | 快速CMOS八端口收發器/寄存器（3態） |
| 文件頁數： | 1/8頁 |
| 文件大?。?/td> | 91K |
| 代理商： | IDT54FCT646CTP |
Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
MAY 1992
1992 Integrated Device Technology, Inc.
7.18
DSC-4626/2
1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a registered trademark of National Semiconductor Co.
IDT54/74FCT646
IDT54/74FCT646A
IDT54/74FCT646C
FEATURES:
IDT54/74FCT646 equivalent to FAST
speed;
IDT54/74FCT646A 30% faster than FAST
IDT54/74FCT646C 40% faster than FAST
Independent registers for A and B buses
Multiplexed real-time and stored data
I
OL
= 64mA (commercial) and 48mA (military)
CMOS power levels (1mW typical static)
TTL input and output level compatible
CMOS output level compatible
Available in 24-pin (300 mil) CERDIP, plastic DIP, SOIC,
CERPACK and 28-pin LCC
Product available in Radiation Tolerant and Radiation
Enhanced Versions
Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT54/74FCT646/A/C consists of a bus transceiver
with 3-state D-type flip-flops and control circuitry arranged for
multiplexed transmission of data directly from the data bus or
from the internal storage registers.
The IDT54/74FCT646/A/C utilizes the enable control (
G
)
and direction (DIR) pins to control the transceiver functions.
SAB and SBA control pins are provided to select either real
time or stored data transfer. The circuitry used for select
control will eliminate the typical decoding glitch that occurs in
a multiplexer during the transition between stored and real-
time data. A LOW input level selects real-time data and a
HIGH selects stored data.
Data on the A or B data bus or both can be stored in the
internal D flip flops by LOW-to-HIGH transitions at the
appropriate clock pins (CPAB or CPBA) regardless of the
select or enable control pins.
FAST CMOS OCTAL
TRANSCEIVER/REGISTER
FUNCTIONAL BLOCK DIAGRAM
2536 drw 01
1D
C
1
A REG
A
1
1D
C
1
B REG
B
1
TO 7 OTHER CHANNELS
1 OF 8 CHANNELS
SAB
CPBA
CPAB
SBA
DIR
G
相關PDF資料 |
PDF描述 |
|---|---|
| IDT54FCT646CTPB | FAST CMOS OCTAL TRANSCEIVER/ REGISTERS (3-STATE) |
| IDT54FCT646CTPG | FAST CMOS OCTAL TRANSCEIVER/ REGISTERS (3-STATE) |
| IDT54FCT646CTPY | FAST CMOS OCTAL TRANSCEIVER/ REGISTERS (3-STATE) |
| IDT54FCT646CTPYB | FAST CMOS OCTAL TRANSCEIVER/ REGISTERS (3-STATE) |
| IDT54FCT646CTQ | FAST CMOS OCTAL TRANSCEIVER/ REGISTERS (3-STATE) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| IDT54FCT648ATLM | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT54FCT821ADB | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT54FCT821BDB | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT54FCT821HATEB | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT54FCT821HCTEB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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