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參數資料
型號: IDT54FCT823CTL
廠商: Integrated Device Technology, Inc.
英文描述: HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
中文描述: 高性能CMOS總線接口寄存器
文件頁數: 1/9頁
文件大小: 178K
代理商: IDT54FCT823CTL
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT821AT/BT/CT
IDT54/74FCT823AT/BT/CT/DT
IDT54/74FCT825AT/BT/CT
Integrated Device Technology, Inc.
1
HIGH-PERFORMANCE
CMOS BUS
INTERFACE REGISTERS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FEATURES:
Common features:
Low input and output leakage
1
μ
A (max.)
CMOS power levels
True TTL input and output compatibility
– V
OH
= 3.3V (typ.)
– V
OL
= 0.3V (typ.)
Meets or exceeds JEDEC standard 18 specifications
Product available in Radiation Tolerant and Radiation
Enhanced versions
Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
Available in DIP, SOIC, SSOP, QSOP, CERPACK
and LCC packages
Features for FCT821T/FCT823T/FCT825T:
A, B, C and D speed grades
High drive outputs (-15mA I
OH
, 48mA I
OL
)
Power off disable outputs permit “live insertion”
DESCRIPTION:
The FCT82xT series is built using an advanced dual metal
CMOS technology. The FCT82xT series bus interface regis-
ters are designed to eliminate the extra packages required to
buffer existing registers and provide extra data width for wider
address/data paths or buses carrying parity. The FCT821T
are buffered, 10-bit wide versions of the popular FCT374T
function. The FCT823T are 9-bit wide buffered registers with
Clock Enable (
EN
) and Clear (
CLR
) – ideal for parity bus
interfacing in high-performance microprogrammed systems.
The FCT825T are 8-bit buffered registers with all the FCT823T
controls plus multiple enables (
OE
1,
OE
2,
OE
3) to allow multi-
user control of the interface, e.g.,
CS
, DMA and RD/
WR
. They
are ideal for use as an output port requiring high I
OL
/I
OH
.
The FCT82xT high-performance interface family can drive
large capacitive loads, while providing low-capacitance bus
loading at both inputs and outputs. All inputs have clamp
diodes and all outputs are designed for low-capacitance bus
loading in high-impedance state.
AUGUST 1995
1995 Integrated Device Technology, Inc
6.21
DSC-4202/5
FUNCTIONAL BLOCK DIAGRAM
D
CPQ
Q
CL
D
CPQ
Q
CL
D
0
D
N
Y
0
Y
N
EN
CLR
CP
OE
2567 drw 01
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