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參數資料
| 型號： | IDT5V9351PRI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | LOW VOLTAGE PLL CLOCK DRIVER |
| 中文描述： | PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | TQFP-32 |
| 文件頁數： | 1/10頁 |
| 文件大小： | 85K |
| 代理商： | IDT5V9351PRI |
INDUSTRIAL TEMPERATURE RANGE
IDT5V9351
LOW VOLTAGE PLL CLOCK DRIVER
1
MARCH 2003
IDT5V9351
INDUS T RIAL T E MPE RAT URE RANGE
LOW VOLTAGE PLL
CLOCK DRIVER
DESCRIPTION:
The IDT5V9351 is a high performance, zero delay, low skew, phase-lock
loop (PLL) clock driver. It has four banks of configurable outputs. The
IDT5V9351 uses a differential PECL reference input and an external feedback
input. These features allow the IDT5V9351 to be used as a zero delay, low
skew fan-out buffer. REF_SEL allows selection between PECL input or TCLK,
a CMOS clock driver input.
If PLL_EN is set to low and REF_SEL to high, it will bypass the PLL. By doing
so, the IDT5V9351 will be in clock buffer mode. Any clock applied to TCLK will
be divided down to four output banks.
When PLL_EN is set high, PLL is enabled. Any clock applied to TCLK will
be clocked in both phase and frequency to FBIN. PECL clock is activated by
setting REF_SEL to low.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2003 Integrated Device Technology, Inc.
DSC-5972/16
FEATURES:
Fully integrated PLL
Output frequency up to 200MHz
2.5V and 3.3V Compatible
Compatible with PowerPC, Intel, and high performance RISC
microprocessors
Output frequency configurable
Cycle-to-cycle jitter max. 22ps RMS
Compatible with MPC9351
Available in TQFP package
FUNCTIONAL BLOCK DIAGRAM
Q
D
2
Q
D
3
Q
D
4
Q
D
1
Q
D
0
Q
C
0
Q
C
1
Q
B
Q
A
÷
2
÷
4
÷
8
1
0
1
0
1
0
D
Q
D
Q
D
Q
D
Q
1
0
f
SELA
f
SELB
f
SELC
f
SELD
PECL_CLK
PECL_CLK
PLL_En
t
CLK
REF_
SEL
OE
FBIN
1
0
(pullup)
(pulldown)
(pulldown)
200 - 400MHz
REF
PLL
FB
1
0
(pulldown)
(pulldown)
(pullup)
(pulldown)
(pulldown)
(pulldown)
(pulldown)
相關PDF資料 |
PDF描述 |
|---|---|
| IDT5V9351 | LOW VOLTAGE PLL CLOCK DRIVER |
| IDT5V9351PR | LOW VOLTAGE PLL CLOCK DRIVER |
| IDT5V9352 | 3.3V/2.5V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER |
| IDT5V9352PRI | 3.3V/2.5V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER |
| IDT5V9910A-7SOI | 3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR |
相關代理商/技術參數 |
參數描述 |
|---|---|
| IDT5V9352PFGI | 功能描述:IC BUFFER ZD PLL CLK DVR 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數:- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| IDT5V9352PFGI8 | 功能描述:IC BUFFER ZD PLL CLK DVR 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數:- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| IDT5V9855-003PFI | 制造商:INT_DEV_TECH 功能描述: |
| IDT5V9885ANLGI | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT5V9885BNLGI | 功能描述:IC CLK GEN 3.3V EEPROM 28-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數:1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
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