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參數(shù)資料
| 型號(hào)： | IDT7007L35PFI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | DRAM |
| 英文描述： | HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM |
| 中文描述： | 32K X 8 DUAL-PORT SRAM, 35 ns, PQFP80 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, TQFP-80 |
| 文件頁(yè)數(shù)： | 1/21頁(yè) |
| 文件大小： | 257K |
| 代理商： | IDT7007L35PFI |
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1
JUNE 1999
DSC 2940/8
I/O
Control
Address
Decoder
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
Address
Decoder
I/O
Control
R/
W
L
CE
L
OE
L
BUSY
L
A
14L
A
0L
2940 drw 01
I/O
0L
- I/O
7L
CE
L
OE
L
R/
W
L
SEM
L
INT
L
M/
S
BUSY
R
I/O
0R
-I/O
7R
A
14R
A
0R
SEM
R
INT
R
CE
R
OE
R
R/
W
R
(2)
(1,2)
(1,2)
(2)
R/
W
R
CE
R
OE
R
15
15
HIGH-SPEED
32K x 8 DUAL-PORT
STATIC RAM
Features
N
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
N
High-speed access
Military: 25/35/55ns (max.)
Industrial: 55ns (max.)
Commercial: 15/20/25/35/55ns (max.)
N
Low-power operation
IDT7007S
Active: 850mW (typ.)
Standby: 5mW (typ.)
IDT7007L
Active: 850mW (typ.)
Standby: 1mW (typ.)
N
IDT7007 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
one device
N
M/
S
= H for
BUSY
output flag on Master,
M/
S
= L for
BUSY
input on Slave
N
Interrupt Flag
N
On-chip port arbitration logic
N
Full on-chip hardware support of semaphore signaling
between ports
N
Fully asynchronous operation from either port
N
TTL-compatible, single 5V (±10%) power supply
N
Available in 68-pin PGA and PLCC and a 80-pin TQFP
N
Industrial temperature range (40°C to +85°C) is available
for selected speeds
NOTES:
1. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
2.
BUSY
and
INT
outputs are non-tri-stated push-pull.
Functional Block Diagram
IDT7007S/L
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