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參數資料
| 型號： | IDT70104S55P |
| 英文描述： | x9 Dual-Port SRAM |
| 中文描述： | X9熱賣雙端口SRAM |
| 文件頁數： | 1/15頁 |
| 文件大小： | 190K |
| 代理商： | IDT70104S55P |
2000 Integrated Device Technology, Inc.
JANUARY 2001
DSC-4857/2
1
Functional Block Diagram
Features:
x
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
x
High-speed clock to data access
– Commercial: 7.5/9/12ns (max.)
x
Low-power operation
– IDT70V9379L
Active: 500mW (typ.)
Standby: 1.5mW (typ.)
x
Flow-Through or Pipelined output mode on either port via
the
FT/PIPE pins
x
Counter enable and reset features
x
Dual chip enables allow for depth expansion without
additional logic
x
Full synchronous operation on both ports
– 4ns setup to clock and 0ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 7.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 12ns cycle time, 83MHz operation in Pipelined output mode
x
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
x
LVTTL- compatible, single 3.3V (±0.3V) power supply
x
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
x
Available in a 128-pin Thin Quad Flatpack (TQFP)
IDT70V9379L
0a 1a
0b 1b
0/1
ab
I/O
Control
1
0/1
0
FT/PIPER
R/WR
UBR
LBR
CE0R
OER
CE1R
MEMORY
ARRAY
Counter/
Address
Reg.
4857 drw 01
A14R
A0R
CLKR
ADSR
CNTENR
CNTRSTR
I/O9L-I/O17L
I/O0L-I/O8L
I/O9R-I/O17R
I/O0R-I/O8R
A0L
CLKL
ADSL
A14L
CNTENL
CNTRSTL
Counter/
Address
Reg.
R/WL
UBL
LBL
CE0L
OEL
CE1L
1
0/1
0
1b 0b
1a 0a
0/1
ba
I/O
Control
FT/PIPEL
HIGH-SPEED 3.3V 32K x 18
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
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