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參數資料
| 型號： | IDT70125S55JGI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
| 中文描述： | 高速2K × 9雙端口靜態RAM繁忙 |
| 文件頁數： | 1/15頁 |
| 文件大小： | 139K |
| 代理商： | IDT70125S55JGI |
2006 Integrated Device Technology, Inc.
APRIL 2006
DSC 2654/10
1
I/O
Control
Address
Decoder
MEMORY
ARRAY
ARBITRATION
INTERRUPT
LOGIC
Address
Decoder
I/O
Control
R/
W
L
CE
L
OE
L
BUSY
L
A
10L
A
0L
2654 drw 01
I/O
0L
- I/O
8L
CE
L
OE
L
R/
W
L
INT
L
BUSY
R
I/O
0R
-I/O
8R
A
10R
A
0R
INT
R
CE
R
OE
R
R/
W
R
(2)
(1,2)
(1,2)
(2)
R/
W
R
CE
R
OE
R
11
11
HIGH-SPEED
2K x 9 DUAL-PORT
STATIC RAM
WITH BUSY & INTERRUPT
IDT70121S/L
IDT70125S/L
NOTES:
1. 70121 (MASTER):
BUSY
is non-tri-stated push-pull output.
70125 (SLAVE):
BUSY
is input.
2.
INT
is non-tri-stated push-pull output.
Func tional Bloc k Diagram
Features
High-speed access
– Commercial: 25/35/45/55ns (max.)
– Industrial: 35ns (max.)
◆
Low-power operation
– IDT70121/70125S
Active: 675mW (typ.)
Standby: 5mW (typ.)
– IDT70121/70125L
Active: 675mW (typ.)
Standby: 1mW (typ.)
◆
Fully asychronous operation from either port
◆
MASTER IDT70121 easily expands data bus width to 18 bits or
more using SLAVE IDT70125 chip
◆
On-chip port arbitration logic (IDT70121 only)
◆
BUSY
output flag on Master;
BUSY
input on Slave
◆
INT
flag for port-to-port communication
◆
Battery backup operation—2V data retention
◆
TTL-compatible, signal 5V (±10%) power supply
◆
Available in 52-pin PLCC
◆
Industrial temperature range (–40°C to +85°C) is available for
selected speeds
◆
Green parts available, see ordering information
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