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參數(shù)資料
| 型號(hào)： | IDT7142SA25PI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS |
| 中文描述： | 2K X 8 DUAL-PORT SRAM, 25 ns, PDIP48 |
| 封裝： | 0.550 X 2.430 INCH, 0.180 INCH HEIGHT, PLASTIC, DIP-48 |
| 文件頁數(shù)： | 1/16頁 |
| 文件大小： | 255K |
| 代理商： | IDT7142SA25PI |
1
2004 Integrated Device Technology, Inc.
JUNE 2004
DSC-2692/16
HIGH SPEED
2K x 8 DUAL PORT
STATIC RAM
IDT7132SA/LA
IDT7142SA/LA
Functional Block Diagram
Features
◆
High-speed access
– Commercial: 20/25/35/55/100ns (max.)
– Industrial: 25ns (max.)
– Military: 25/35/55/100ns (max.)
◆
Low-power operation
– IDT7132/42SA
Active: 325mW (typ.)
Standby: 5mW (typ.)
– IDT7132/42LA
Active: 325mW (typ.)
Standby: 1mW (typ.)
NOTES:
1. IDT7132 (MASTER):
BUSY
is open drain output and requires pullup resistor of 270
.
IDT7142 (SLAVE):
BUSY
is input.
2. Open drain output: requires pullup resistor of 270
.
◆
MASTER IDT7132 easily expands data bus width to 16-or-more
bits using SLAVE IDT7142
◆
On-chip port arbitration logic (IDT7132 only)
◆
BUSY
output flag on IDT7132;
BUSY
input on IDT7142
◆
Battery backup operation —2V data retention (LA only)
◆
TTL-compatible, single 5V ±10% power supply
◆
Available in 48-pin DIP, LCC and Flatpack, and 52-pin PLCC
packages
◆
Military product compliant to MIL-PRF-38535 QML
◆
Industrial temperature range (–40°C to +85°C) is available for
selected speeds
OE
L
CE
L
R/W
L
I/O
OL-
I/O
7L
BUSY
L
(1,2)
A
10L
A
0L
CE
L
OE
L
R/
W
L
CE
R
OE
R
R/
W
R
OE
R
CE
R
R/
W
R
I/O
OR-
I/O
7R
BUSY
R
(1,2)
A
10R
A
0R
I/O
Control
I/O
Control
Address
Decoder
Address
Decoder
MEMORY
ARRAY
ARBITRATION
LOGIC
2692 drw 01
m
11
11
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