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參數資料
型號: IDT72251L35J
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: CMOS SyncFIFOO 8192 X 9
中文描述: 8K X 9 OTHER FIFO, 20 ns, PQCC32
封裝: PLASTIC, LCC-32
文件頁數: 1/17頁
文件大小: 183K
代理商: IDT72251L35J
Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGES
DECEMBER 1996
1996 Integrated Device Technology, Inc
DSC-3545/-
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
8192 x 9-bit organization
Pin/function compatible with IDT72421/722x1 family
15 ns read/write cycle time
Read and write clocks can be independent
Dual-Ported zero fall-through time architecture
Empty and Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags can
be set to any depth
Programmable Almost-Empty and Almost-Full flags
default to Empty+7, and Full-7, respectively
Output enable puts output data bus in high-impedance
state
Advanced submicron CMOS technology
Available in 32-pin plastic leaded chip carrier (PLCC)
Industrial temperature range (-40
o
C to +85
o
C) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT72251 SyncFIFO
is a very high-speed, low-
power First-In, First-Out (FIFO) memory with clocked read
and write controls. The IDT72251 has a 8192 x 9-bit memory
array. This FIFO is applicable for a wide variety of data
buffering needs such as graphics, local area networks and
FUNCTIONAL BLOCK DIAGRAM
WCLK
WEN2
D
0
- D
8
OFFSET REGISTER
INPUT REGISTER
RAM ARRAY
8192 x 9
WRITE CONTROL
LOGIC
WRITE POINTER
RESET LOGIC
OUTPUT REGISTER
Q
0
- Q
8
RCLK
READ CONTROL
LOGIC
READ POINTER
FLAG
LOGIC
3545 drw 01
interprocessor communication.
This FIFO has a 9-bit input and output port. The input port
is controlled by a free-running clock (WCLK), and two write
enable pins (
WEN1
, WEN2). Data is written into the
Synchronous FIFO on every rising clock edge when the write
enable pins are asserted. The output port is controlled by
another clock pin (RCLK) and two read enable pins (
REN1
,
REN2
). The read clock can be tied to the write clock for single
clock operation or the two clocks can run asynchronous of one
another for dual-clock operation. An output enable pin (
OE
) is
provided on the read port for three-state control of the output.
The Synchronous FIFO has two fixed flags, Empty (
EF
) and
Full (
FF
). Two programmable flags, Almost-Empty (
PAE
) and
Almost-Full (
PAF
), are provided for improved system control.
The programmable flags default to Empty+7 and Full-7 for
PAE
and
PAF
, respectively. The programmable flag offset
loading is controlled by a simple state machine and is initiated
by asserting the load pin (
LD
).
The IDT72251 is fabricated using IDT’s high-speed
submicron CMOS technology.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.14
CMOS SyncFIFO
8192 X 9
ADVANCED
INFORMATION
IDT72251
1
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IDT72255LA10PF8 功能描述:IC FIFO 8KX18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K(16K x 18) 數據速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP(14x14) 包裝:托盤 其它名稱:72271LA10PF
IDT72255LA10PFG 功能描述:IC FIFO 8KX18 LP 10NS 64QFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K(16K x 18) 數據速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP(14x14) 包裝:托盤 其它名稱:72271LA10PF
IDT72255LA10PFG8 功能描述:IC FIFO 8KX18 LP 10NS 64QFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K(16K x 18) 數據速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP(14x14) 包裝:托盤 其它名稱:72271LA10PF
IDT72255LA10TF 功能描述:IC FIFO 8KX18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K(16K x 18) 數據速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP(14x14) 包裝:托盤 其它名稱:72271LA10PF
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