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參數資料
| 型號： | IDT72256LA10PFI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | CMOS SUPERSYNC FIFO |
| 中文描述： | 先進先出的CMOS SUPERSYNC |
| 文件頁數： | 1/27頁 |
| 文件大小： | 354K |
| 代理商： | IDT72256LA10PFI |
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COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
APRIL 2001
2001 Integrated Device Technology, Inc
DSC-4670/1
1
Integrated Device Technology, Inc.
SuperSyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
Choose among the following memory organizations:
IDT72255LA
8,192 x 18
IDT72265LA
16,384 x 18
Pin-compatible with the IDT72275/72285 SuperSync FIFOs
10ns read/write cycle time (8ns access time)
Fixed, low first word data latency time
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable
settings
Retransmit operation with fixed, low first word data
latency time
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags, each
flag can default to one of two preselected offsets
Program partial flags by either serial or parallel means
Select IDT Standard timing (using
EF
and
FF
flags) or First
Word Fall Through timing (using
OR
and
IR
flags)
Output enable puts data outputs into high impedance state
Easily expandable in depth and width
Independent Read and Write clocks (permit reading and
writing simultaneously)
Available in the 64-pin Thin Quad Flat Pack (TQFP) and the
64-pin Slim Thin Quad Flat Pack (STQFP)
High-performance submicron CMOS technology
Industrial temperature range (–40
°
C to +85
°
C) is available
DESCRIPTION:
The IDT72255LA/72265LA are exceptionally deep, high
speed, CMOS First-In-First-Out (FIFO) memories with clocked
read and write controls. These FIFOs offer numerous improve-
ments over previous SuperSync FIFOs, including the following:
The limitation of the frequency of one clock input with
respect to the other has been removed. The Frequency
Select pin (FS) has been removed, thus it is no longer
necessary to select which of the two clock inputs, RCLK or
WCLK, is running at the higher frequency.
The period required by the retransmit operation is now fixed
and short.
FUNCTIONAL BLOCK DIAGRAM
IDT72255LA
IDT72265LA
CMOS SUPERSYNC FIFO
8,192 x 18
16,384 x 18
INPUT REGISTER
OUTPUT REGISTER
RAM ARRAY
8,192 x 18
16,384 x 18
FLAG
LOGIC
/
/
READ POINTER
READ
CONTROL
LOGIC
WRITE CONTROL
LOGIC
WRITE POINTER
RESET
LOGIC
WCLK
D
0
-D
17
RCLK
Q
0
-Q
17
OFFSET REGISTER
FWFT/SI
4670 drw 01
相關PDF資料 |
PDF描述 |
|---|---|
| IDT72256LA10TF | CMOS SUPERSYNC FIFO |
| IDT72261 | CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9 |
| IDT72261L10G | CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9 |
| IDT72261L10GB | CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9 |
| IDT72261L10PF | CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| IDT7225LB25J | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT72261LA10PF | 功能描述:IC FIFO 8192X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數據速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72261LA10PF8 | 功能描述:IC FIFO 8192X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數據速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72261LA10TF | 功能描述:IC FIFO 8192X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數據速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72261LA10TF8 | 功能描述:IC FIFO 8192X18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數據速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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