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參數資料
| 型號： | IDT72265L15G |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS SUPERSYNC FIFOO 8,192 x 18, 16,384 x 18 |
| 中文描述： | 16K X 18 OTHER FIFO, CPGA68 |
| 封裝： | PGA-68 |
| 文件頁數： | 1/30頁 |
| 文件大小： | 394K |
| 代理商： | IDT72265L15G |
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MILITARY AND COMMERCIAL TEMPERATURE RANGES
MAY 1997
1997 Integrated Device Technology, Inc
DSC-3037/7
1
Integrated Device Technology, Inc.
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
FUNCTIONAL BLOCK DIAGRAM
INPUT REGISTER
OUTPUT REGISTER
RAM ARRAY
8,192 x 18
16,384 x 18
FLAG
LOGIC
FF
/
IR
PAF
EF
/
OR
PAE
HF
FWFT/SI
READ POINTER
READ
CONTROL
LOGIC
WRITE CONTROL
LOGIC
WRITE POINTER
RESET
LOGIC
WEN
WCLK
D
0
-D
17
LD
MRS
REN
RCLK
OE
Q
0
-Q
17
TIMING
FS
OFFSET REGISTER
PRS
SEN
RT
3037 drw 01
IDT72255
IDT72265
CMOS SUPERSYNC FIFO
8,192 x 18, 16,384 x 18
FEATURES:
8,192 x 18-bit storage capacity (IDT72255)
16,384 x 18-bit storage capacity (IDT72265)
10ns read/write cycle time (8ns access time)
Retransmit Capability
Auto power down reduces power consumption
Master Reset clears entire FIFO, Partial Reset clears
data, but retains programmable settings
Empty, Full and Half-full flags signal FIFO status
Programmable Almost Empty and Almost Full flags, each
flag can default to one of two preselected offsets
Program partial flags by either serial or parallel means
Select IDT Standard timing (using
EF
and
FF
flags) or
First Word Fall Through timing (using
OR
and
IR
flags)
Easily expandable in depth and width
Independent read and write clocks (permit simultaneous
reading and writing with one clock signal)
Available in the 64-pin Thin Quad Flat Pack (TQFP), 64-
pin Slim Thin Quad Flat Pack (STQFP) and the 68-pin
Pin Grid Array (PGA)
Output enable puts data outputs into high impedance
High-performance submicron CMOS technology
Industrial temperature range (-40
o
C to +85
o
C) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT72255/72265 are monolithic, CMOS, high capac-
ity, high speed, low power First-In, First-Out (FIFO) memories
with clocked read and write controls. These FIFOs are appli-
cable for a wide variety of data buffering needs, such as optical
disk controllers, local area networks (LANs), and inter-proces-
sor communication.
Both FIFOs have an 18-bit input port (D
n
) and an 18-bit
output port (Q
n
). The input port is controlled by a free-running
clock (WCLK) and a data input enable pin (
WEN
). Data is
written into the synchronous FIFO on every clock when
WEN
is asserted. The output port is controlled by another clock pin
(RCLK) and enable pin (
REN
). The read clock can be tied to
the write clock for single clock operation or the two clocks can
run asynchronously for dual clock operation. An output enable
pin (
OE
) is provided on the read port for three-state control of
the outputs.
The IDT72255/72265 have two modes of operation: In the
IDT Standard Mode
, the first word written to the FIFO is
deposited into the memory array. A read operation is required
to access that word. In the
First Word Fall Through Mode
(FWFT), the first word written to an empty FIFO appears
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
相關PDF資料 |
PDF描述 |
|---|---|
| IDT72265L15GB | CMOS SUPERSYNC FIFOO 8,192 x 18, 16,384 x 18 |
| IDT72274 | VARIABLE WIDTH SUPERSYNCO FIFO 8,192 x 18 or 16,384 x 9 16,384 x 18 or 32,768 x 9 |
| IDT72274L15G | VARIABLE WIDTH SUPERSYNCO FIFO 8,192 x 18 or 16,384 x 9 16,384 x 18 or 32,768 x 9 |
| IDT72274L15PF | WAVEGUIDE ADAPTER; WAVEGUIDE TO 7mm; WAVEGUIDE: WR-62; FREQUENCY RANGE: 12.40 - 18.00 GHz |
| IDT72274L15TF | WAVEGUIDE ADAPTER; WAVEGUIDE TO 7mm; WAVEGUIDE: WR-90; FREQUENCY RANGE: 8.20 - 12.40 GHz |
相關代理商/技術參數 |
參數描述 |
|---|---|
| IDT72265LA10PF | 功能描述:IC FIFO 8KX18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數據速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72265LA10PF8 | 功能描述:IC FIFO 8KX18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數據速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72265LA10PFG | 功能描述:IC FIFO SUPERSYNC 8KX18 64QFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:74ABT 功能:同步，雙端口 存儲容量:4.6K（64 x 36 x2） 數據速率:67MHz 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:120-LQFP 裸露焊盤 供應商設備封裝:120-HLQFP（14x14） 包裝:托盤 產品目錄頁面:1005 (CN2011-ZH PDF) 其它名稱:296-3984 |
| IDT72265LA10TF | 功能描述:IC FIFO 8KX18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數據速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72265LA10TF8 | 功能描述:IC FIFO 8KX18 LP 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數據速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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