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參數(shù)資料
| 型號： | IDT72T18115L6-7BBI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 2.5 VOLT HIGH-SPEED TeraSync FIFO 18-BIT/9-BIT CONFIGURATIONS |
| 中文描述： | 2.5伏高速TeraSync先進(jìn)先出18-BIT/9-BIT配置 |
| 文件頁數(shù)： | 1/55頁 |
| 文件大小： | 540K |
| 代理商： | IDT72T18115L6-7BBI |
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1
SEPTEMBER 2003
DSC-5909/16
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
2.5 VOLT HIGH-SPEED TeraSync FIFO
18-BIT/9-BIT CONFIGURATIONS
2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9, 8,192 x 18/16,384 x 9,
16,384 x 18/32,768 x 9, 32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9,
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9, 524,288 x 18/1,048,576 x 9
IDT72T1845, IDT72T1855
IDT72T1865, IDT72T1875
IDT72T1885, IDT72T1895
IDT72T18105, IDT72T18115
IDT72T18125
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. TeraSync FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FEATURES:
Choose among the following memory organizations:
IDT72T1845
2,048 x 18/4,096 x 9
IDT72T1855
4,096 x 18/8,192 x 9
IDT72T1865
8,192 x 18/16,384 x 9
IDT72T1875
16,384 x 18/32,768 x 9
IDT72T1885
32,768 x 18/65,536 x 9
IDT72T1895
65,536 x 18/131,072 x 9
IDT72T18105
131,072 x 18/262,144 x 9
IDT72T18115
262,144 x 18/524,288 x 9
IDT72T18125
524,288 x 18/1,048,576 x 9
Up to 225 MHz Operation of Clocks
User selectable HSTL/LVTTL Input and/or Output
Read Enable & Read Clock Echo outputs aid high speed operation
User selectable Asynchronous read and/or write port timing
2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage
3.3V Input tolerant
Mark & Retransmit, resets read pointer to user marked position
Write Chip Select (
WCS
) input enables/disables Write operations
Read Chip Select (
RCS
) synchronous to RCLK
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
Program programmable flags by either serial or parallel means
Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
Separate SCLK input for Serial programming of flag offsets
User selectable input and output port bus-sizing
- x9 in to x9 out
- x9 in to x18 out
- x18 in to x9 out
- x18 in to x18 out
Big-Endian/Little-Endian user selectable byte representation
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Empty, Full and Half-Full flags signal FIFO status
Select IDT Standard timing (using
EF
and
FF
flags) or First Word
Fall Through timing (using
OR
and
IR
flags)
Output enable puts data outputs into high impedance state
JTAG port, provided for Boundary Scan function
Available in 144-pin (13mm x 13mm) or 240-pin (19mm x 19mm)
PlasticBall Grid Array (PBGA)
Easily expandable in depth and width
Independent Read and Write Clocks (permit reading and writing
simultaneously)
High-performance submicron CMOS technology
Industrial temperature range (–40
°
C to +85
°
C) is available
INPUT REGISTER
OUTPUT REGISTER
RAM ARRAY
2,048 x 18 or 4,096 x 9
4,096 x 18 or 8,192 x 9
8,192 x 18 or 16,384 x 9
16,384 x 18 or 32,768 x 9
32,768 x 18 or 65,536 x 9
65,536 x 18 or 131,072 x 9
131,072 x 18 or 262,144 x 9
262,144 x 18 or 524,288 x 9
524,288 x 18 or 1,048,576 x 9
FLAG
LOGIC
FF
/
IR
PAF
EF
/
OR
PAE
HF
FWFT/SI
PFM
FSEL0
FSEL1
READ POINTER
READ
CONTROL
LOGIC
WRITE CONTROL
LOGIC
WRITE POINTER
RESET
LOGIC
WEN
WCLK/WR
D
0
-D
n
(x18 or x9)
LD
MRS
REN
RCLK/RD
OE
Q
0
-Q
n
(x18 or x9)
OFFSET REGISTER
PRS
SEN
RT
MARK
ASYR
5909 drw01
BUS
CONFIGURATION
CONTROL
LOGIC
BE
IP
OW
IW
SCLK
RCS
JTAG CONTROL
(BOUNDARY SCAN)
TCK
TRST
TMS
TDO
TDI
WCS
ERCLK
EREN
HSTL I/0
CONTROL
Vref
WHSTL
RHSTL
SHSTL
ASYW
FUNCTIONAL BLOCK DIAGRAM
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72T18125L6-7BBI | 2.5 VOLT HIGH-SPEED TeraSync FIFO 18-BIT/9-BIT CONFIGURATIONS |
| IDT72T20108 | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
| IDT72T2098L4BBI | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
| IDT72T2098L5BB | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
| IDT72T2098L5BBI | 2.5 VOLT HIGH-SPEED TeraSync⑩ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72T18125L10BB | 功能描述:IC FIFO 524X18 2.5V 10NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:90 系列:74ABT 功能:同步，雙端口 存儲(chǔ)容量:4.6K（64 x 36 x2） 數(shù)據(jù)速率:67MHz 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:120-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:120-HLQFP（14x14） 包裝:托盤 產(chǎn)品目錄頁面:1005 (CN2011-ZH PDF) 其它名稱:296-3984 |
| IDT72T18125L4-4BB | 功能描述:IC FIFO 524X18 2.5V 4NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T18125L4-4BBG | 功能描述:IC FIFO 524X18 2.5V 4NS 240BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:90 系列:74ABT 功能:同步，雙端口 存儲(chǔ)容量:4.6K（64 x 36 x2） 數(shù)據(jù)速率:67MHz 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:120-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:120-HLQFP（14x14） 包裝:托盤 產(chǎn)品目錄頁面:1005 (CN2011-ZH PDF) 其它名稱:296-3984 |
| IDT72T18125L5BB | 功能描述:IC FIFO 524X18 2.5V 5NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T18125L5BBGI | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 524X18 2.5V 5NS 240BGA |
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