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參數資料
| 型號： | IDT72V265LA |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 3.3 VOLT CMOS SuperSync FIFO 8,192 x 18 16,384 x 18 |
| 中文描述： | 3.3伏的CMOS SuperSync先進先出8192 × 18 16,384 × 18 |
| 文件頁數： | 1/27頁 |
| 文件大小： | 439K |
| 代理商： | IDT72V265LA |
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FEATURES:
Choose among the following memory organizations:
IDT72V255LA
8,192 x 18
IDT72V265LA
16,384 x 18
Pin-compatible with the IDT72V275/72V285 and IDT72V295/
72V2105 SuperSync FIFOs
Functionally compatible with the 5 Volt IDT72255/72265 family
10ns read/write cycle time (6.5ns access time)
Fixed, low first word data latency time
5V input tolerant
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Retransmit operation with fixed, low first word data
latency time
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags, each flag
can default to one of two preselected offsets
Program partial flags by either serial or parallel means
Select IDT Standard timing (using EF and FF flags) or First
Word Fall Through timing (using
OR and IR flags)
Output enable puts data outputs into high impedance state
Easily expandable in depth and width
Independent Read and Write clocks (permit reading and
writing simultaneously)
Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-
pin Slim Thin Quad Flat Pack (STQFP)
High-performance submicron CMOS technology
Industrial temperature range (–40°C to +85°C) is available
DESCRIPTION:
The IDT72V255LA/72V265LA are functionally compatible versions of the
IDT72255/72265 designed to run off a 3.3V supply for very low power
consumption. The IDT72V255LA/72V265LA are exceptionally deep, high
speed, CMOS First-In-First-Out (FIFO) memories with clocked read and
write controls. These FIFOs offer numerous improvements over previous
SuperSync FIFOs, including the following:
The limitation of the frequency of one clock input with respect to the other
has been removed. The Frequency Select pin (FS) has been removed,
thus it is no longer necessary to select which of the two clock inputs, RCLK
or WCLK, is running at the higher frequency.
INPUT REGISTER
OUTPUT REGISTER
RAM ARRAY
8,192 x 18
16,384 x 18
FLAG
LOGIC
FF/IR
PAF
EF/OR
PAE
HF
READ POINTER
READ
CONTROL
LOGIC
WRITE CONTROL
LOGIC
WRITE POINTER
RESET
LOGIC
WEN
WCLK
D0 -D17
LD
MRS
REN
RCLK
OE
Q0 -Q17
OFFSET REGISTER
PRS
FWFT/SI
SEN
RT
4672 drw 01
IDT72V255LA
IDT72V265LA
3.3 VOLT CMOS SuperSync FIFO
8,192 x 18
16,384 x 18
APRIL 2001
2001 Integrated Device Technology, Inc
DSC-4672/1
The IDT logo is a registered trademark and the SuperSyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FUNCTIONAL BLOCK DIAGRAM
1
相關PDF資料 |
PDF描述 |
|---|---|
| IDT72V271LA20TFI | Octal D-type flip-flop; positive edge-trigger; 3-state - Description: D-Type Flip-Flop; Postive-Edge Trigger (3-State) ; F<sub>max</sub>: 185 @ 5 V MHz; Logic switching levels: CMOS ; Output drive capability: +/- 8 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 4.4@5V ns; Voltage: 2.0-5.5 V |
| IDT72V273 | Octal D-type flip-flop with data enable; positive-edge trigger - Description: Octal D-Type Flip-Flop with Data Enable; Positive-Edge Trigger ; F<sub>max</sub>: 175 @ 5V MHz; Logic switching levels: CMOS ; Output drive capability: +/- 8 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 3.9@5V ns; Voltage: 2.0-5.5 V |
| IDT72V275 | Octal D-type flip-flop with data enable; positive-edge trigger - Description: Octal D-Type Flip-Flop with Data Enable; Positive-Edge Trigger ; F<sub>max</sub>: 175 @ 5V MHz; Logic switching levels: CMOS ; Output drive capability: +/- 8 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 3.9@5V ns; Voltage: 2.0-5.5 V |
| IDT72V281 | Octal D-type flip-flop; positive edge-trigger; 3-state |
| IDT72V281L15TF | 3.3 VOLT CMOS SuperSync FIFOTM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| IDT72V265LA10PF | 功能描述:IC FIFO SS 16384X18 10NS 64-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數據速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V265LA10PF8 | 功能描述:IC FIFO SS 16384X18 10NS 64-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數據速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V265LA10PFG | 功能描述:IC FIFO SS 16384X18 10NS 64-TQFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:90 系列:74ABT 功能:同步，雙端口 存儲容量:4.6K（64 x 36 x2） 數據速率:67MHz 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:120-LQFP 裸露焊盤 供應商設備封裝:120-HLQFP（14x14） 包裝:托盤 產品目錄頁面:1005 (CN2011-ZH PDF) 其它名稱:296-3984 |
| IDT72V265LA10PFG8 | 功能描述:IC FIFO SS 16384X18 10NS 64-TQFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數據速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V265LA10TF | 功能描述:IC FIFO SS 16384X18 10NS 64STQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數據速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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