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參數資料
| 型號： | IDT74823BLSO |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH PERFORMANCE CMOS BUS INTERFACE REGISTER |
| 中文描述： | 高性能CMOS總線接口寄存器 |
| 文件頁數： | 1/7頁 |
| 文件大小： | 89K |
| 代理商： | IDT74823BLSO |
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT823A/B/C
HIGH-PERFORMANCE CMOS BUFFER
1
J UNE 2002
MILIT ARY AND COMMERCIAL T EMPERAT URE RANGES
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2002 Integrated Device Technology, Inc.
DSC-5426/3
FEATURES:
Equivalent to AMD's Am29823 bipolar registers in pinout/
function, speed, and output drive over full temperature and
voltage supply extremes
IDT54/74FCT823A equivalent to FAST speed
IDT54FCT823B 25% faster than FAST
IDT74FCT823C 40% faster than FAST
Buffered common Clock Enable (
EN
) and Asynchronous Clear
Input (
CLR
)
I
OL
= 48mA (commercial) and 32mA (military)
Clamp diodes on all inputs for ringing suppression
CMOS power levels (1mW typ. static)
TTL input and output compatibility
CMOS output level compatible
Substantially lower input current levels than AMD's bilopar
Am29800 series (5
μ
A max.)
MIlitary product compliant to MIL-STD-883, Class B
Available in the following packages:
– Commercial: SOIC
– Mlitary: CERDIP, LCC
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The FCT823 series is built using an advanced dual metal CMOS
technology. The FCT823 bus interface registers are designed to elimnate
the extra packages required to buffer existing registers and provide extra
data width for wider address/data paths or buses carrying parity. The
FCT823 is a 9-bit wide buffered register with Clock Enable (
EN
) and Clear
(
CLR
) – ideal for parity bus interfacing in high-performance mcroprogram-
med systems.
The FCT823 high-performance interface famly is designed for high-
capacitance load drive capability, while providing low-capacitance bus
loading at both inputs and outputs. All inputs have clamp diodes and all
outputs are designed for low-capacitance bus loading in high-impedance
state.
IDT54/74FCT823A/B/C
HIGH PERFORMANCE
CMOS BUS INTERFACE
REGISTER
D
CP
Q
Q
CL
D
N
D
0
D
CP
Q
Q
CL
EN
CLR
CP
OE
Y
0
Y
N
14
11
13
1
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