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參數(shù)資料
| 型號： | IDT74ALVCH16260PAG8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 0K |
| 描述： | IC LATCH 12-24BIT MUX D 56-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | 74ALVCH |
| 邏輯類型： | D 型透明鎖存器 |
| 電路： | 12:24 |
| 輸出類型： | 三態(tài) |
| 電源電壓： | 2.3 V ~ 3.6 V |
| 獨立電路： | 1 |
| 延遲時間 - 傳輸： | 1ns |
| 輸出電流高，低： | 24mA，24mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-TSSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 1257 (CN2011-ZH PDF) |
| 其它名稱： | 800-1555-6 |
INDUSTRIALTEMPERATURERANGE
IDT74ALVCH16260
3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
1
JULY 2009
INDUSTRIAL TEMPERATURE RANGE
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
2009 Integrated Device Technology, Inc.
DSC-4737/6
FEATURES:
0.5 MICRON CMOS Technology
Typical tSK(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
VCC = 2.5V ± 0.2V
CMOS power levels (0.4
μμμμμ W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in TSSOP package
FUNCTIONAL BLOCK DIAGRAM
IDT74ALVCH16260
3.3V CMOS 12-BIT TO 24-BIT
MULTIPLEXED D-TYPE LATCH
WITH 3-STATE OUTPUTS
AND BUS-HOLD
DESCRIPTION:
This 12-bit to 24-bit multiplexed D-type latch is built using advanced dual
metal CMOS technology. The ALVCH16260 is used in applications in which
two separate data paths must be multiplexed onto, or demultiplexed from, a
singledatapath.Typicalapplicationsincludemultiplexingand/ordemultiplexing
addressanddatainformationinmicroprocessororbus-interfaceapplications.
This device also is useful in memory interleaving applications.
Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available
foraddressand/ordatatransfer.Theoutput-enable(
OE1B,OE2B,andOEA)
inputs control the bus transceiver functions. The
OE1B and OE2B control
signals also allow bank control in the A-to-B direction. Address and/or data
informationcanbestoredusingtheinternalstoragelatches.Thelatch-enable
(LE1B, LE2B, LEA1B, and LEA2B) inputs are used to control data storage.
When the latch-enable input is high, the latch is transparent. When the latch-
enable input goes low, the data present at the inputs is latched and remains
latched until the latch-enable input is returned high.
The ALVCH16260 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining speed
performance.
The ALVCH16260 has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
APPLICATIONS:
3.3V high speed systems
3.3V and lower voltage computing systems
DRIVE FEATURES:
High Output Drivers: ±24mA
Suitable for heavy loads
LE1B
LEA1B
OE1B
SEL
OEA
A1:12
LE2B
LEA2B
OE2B
A-1B
LATCH
1B-A
LATCH
A-2B
LATCH
2B-A
LATCH
M
U
X
1
0
12
1
B1:12
2
B1:12
12
30
29
2
28
1
27
55
56
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| IDT74ALVCH162820PAG | 功能描述:IC FLIP FLOP 3ST 10BIT 56TSSOP RoHS:是 類別:集成電路 (IC) >> 邏輯 - 觸發(fā)器 系列:74ALVCH 標(biāo)準(zhǔn)包裝:1 系列:74LVX 功能:主復(fù)位 類型:D 型總線 輸出類型:非反相 元件數(shù):1 每個元件的位元數(shù):8 頻率 - 時鐘:150MHz 延遲時間 - 傳輸:7.1ns 觸發(fā)器類型:正邊沿 輸出電流高，低:4mA，4mA 電源電壓:2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 包裝:Digi-Reel® 其它名稱:74LVX273MTCXDKR |
| IDT74ALVCH162820PAG8 | 功能描述:IC FLIP FLOP 3ST 10BIT 56TSSOP RoHS:是 類別:集成電路 (IC) >> 邏輯 - 觸發(fā)器 系列:74ALVCH 標(biāo)準(zhǔn)包裝:1 系列:74LVX 功能:主復(fù)位 類型:D 型總線 輸出類型:非反相 元件數(shù):1 每個元件的位元數(shù):8 頻率 - 時鐘:150MHz 延遲時間 - 傳輸:7.1ns 觸發(fā)器類型:正邊沿 輸出電流高，低:4mA，4mA 電源電壓:2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 包裝:Digi-Reel® 其它名稱:74LVX273MTCXDKR |
| IDT74ALVCH162825APF | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| IDT74ALVCH16501PA | 制造商:Integrated Device Technology Inc 功能描述:Bus Transceiver, Single, 18 Bit, 56 Pin, Plastic, TSSOP |
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