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參數資料
| 型號： | IDT74LVC373A |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O |
| 中文描述： | 3.3V CMOS電八路透明D類鎖存器三態輸出，5伏的I / O |
| 文件頁數： | 1/6頁 |
| 文件大小： | 70K |
| 代理商： | IDT74LVC373A |
INDUSTRIAL TEMPERATURE RANGE
IDT74LVC373A
3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH
1
OCT OBER 1999
INDUS T RIAL T E MPE RAT URE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
DSC-4640/1
FEATURES:
0.5 MICRON CMOS Technology
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
V
CC
= 3.3V ± 0.3V, Normal Range
V
CC
= 2.7V to 3.6V, Extended Range
CMOS power levels (0.4
μ
W typ. static)
Rail-to-rail output swing for increased noise margin
All inputs, outputs, and I/O are 5V tolerant
Supports hot insertion
Available in SOIC, SSOP, QSOP, and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS:
5V and 3.3V mixed voltage systems
Data communication and telecommunication systems
DRIV E FEATURES:
High Output Drivers: ±24mA
Reduced system switching noise
IDT74LVC373A
DESCRIPTION:
The LVC373A Octal transparent D-type latch is built using advanced dual
metal CMOS technology.
While the latch-enable (LE) input is high, the Q outputs follow the data (D)
inputs. When LE is taken low, the Q outputs are latched at the logic levels
set up at the D inputs.
A buffered output-enable (
OE
) input can be used to place the eight outputs
in either a normal logic state (high or low logic levels) or a high-impedance
state. In the high- impedance state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and increased drive provide
the capability to drive bus lines without interface or pullup components.
OE
does not affect the internal operations of the latch. Old data can be
retained or new data can be entered while the outputs are in the high-
impedance state.
To ensure the high-impedance state during power up or power down,
OE
should be tied to V
CC
through a pullup resistor; the mnimumvalue of the
resistor is determned by the current-sinking capability of the driver.
Inputs can be driven fromeither 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mxed 3.3V/5V systemenvironment.
3.3V CMOS OCTAL
TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS,
5 VOLT TOLERANT I/O
OE
C
1
1
D
LE
1
D
TO SEVEN OTHER CHANNELS
1
11
3
2
1
Q
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相關代理商/技術參數 |
參數描述 |
|---|---|
| IDT74LVC374APG | 制造商:MAJOR 功能描述: |
| IDT74LVC4245APGG | 功能描述:IC BUS TRANSCVR 3-ST 8B 24TSSOP RoHS:是 類別:集成電路 (IC) >> 邏輯 - 變換器 系列:74LVC 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:100 系列:- 邏輯功能:變換器，雙向 位數:2 輸入類型:CMOS 輸出類型:CMOS 數據速率:16Mbps 通道數:2 輸出/通道數目:1 差分 - 輸入:輸出:無/無 傳輸延遲（最大）:15ns 電源電壓:1.65 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:10-UFQFN 供應商設備封裝:10-UTQFN（1.4x1.8） 包裝:管件 |
| IDT74LVC4245APGG8 | 功能描述:IC BUS TRANSCVR 3-ST 8B 24TSSOP RoHS:是 類別:集成電路 (IC) >> 邏輯 - 變換器 系列:74LVC 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:100 系列:- 邏輯功能:變換器，雙向 位數:2 輸入類型:CMOS 輸出類型:CMOS 數據速率:16Mbps 通道數:2 輸出/通道數目:1 差分 - 輸入:輸出:無/無 傳輸延遲（最大）:15ns 電源電壓:1.65 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:10-UFQFN 供應商設備封裝:10-UTQFN（1.4x1.8） 包裝:管件 |
| IDT74LVC4245APYG | 功能描述:IC BUS TRANSCVR 3-ST 8BIT 24SSOP RoHS:是 類別:集成電路 (IC) >> 邏輯 - 變換器 系列:74LVC 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:100 系列:- 邏輯功能:變換器，雙向 位數:2 輸入類型:CMOS 輸出類型:CMOS 數據速率:16Mbps 通道數:2 輸出/通道數目:1 差分 - 輸入:輸出:無/無 傳輸延遲（最大）:15ns 電源電壓:1.65 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:10-UFQFN 供應商設備封裝:10-UTQFN（1.4x1.8） 包裝:管件 |
| IDT74LVC4245APYG8 | 功能描述:IC BUS TRANSCVR 3-ST 8BIT 24SSOP RoHS:是 類別:集成電路 (IC) >> 邏輯 - 變換器 系列:74LVC 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:100 系列:- 邏輯功能:變換器，雙向 位數:2 輸入類型:CMOS 輸出類型:CMOS 數據速率:16Mbps 通道數:2 輸出/通道數目:1 差分 - 輸入:輸出:無/無 傳輸延遲（最大）:15ns 電源電壓:1.65 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:10-UFQFN 供應商設備封裝:10-UTQFN（1.4x1.8） 包裝:管件 |
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