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參數資料
| 型號： | IDT74SSTVN16859PAG8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數： | 1/7頁 |
| 文件大小： | 0K |
| 描述： | IC BUFFER 13-26BIT SSTL 64-TSSOP |
| 產品變化通告： | Product Discontinuation 09/Dec/2011 |
| 標準包裝： | 2,000 |
| 邏輯類型： | 13 位至 26 位寄存緩沖器，帶 SSTL_2 輸入和輸出 |
| 電源電壓： | 2.3 V ~ 2.7 V |
| 位數： | 13，26 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-TFSOP （0.240"，6.10mm 寬） |
| 供應商設備封裝： | 64-TSSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 74SSTVN16859PAG8 |
1
COMMERCIALTEMPERATURERANGE
IDT74SSTVN16859
13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
JANUARY 2004
2004 Integrated Device Technology, Inc.
DSC-6836/14
c
IDT74SSTVN16859
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM
13-BIT TO 26-BIT REGISTERED
BUFFER WITH SSTL I/O
DESCRIPTION:
The SSTVN16859 is a 13-bit to 26-bit registered buffer designed for
2.3V-2.7V VDD for PC1600 - PC2700 and 2.5V-2.7V VDD for PC3200, and
supports low standby operation. All data inputs and outputs are SSTL_2
level compatible with JEDEC standard for SSTL_2.
RESET is an LVCMOS input since it must operate predictably during the
power-up phase. RESET, which can be operated independent of CLK and
CLK, must be held in the low state during power-up in order to ensure
predictable outputs (low state) before a stable clock has been applied.
RESET, when in the low state, will disable all input receivers, reset all
registers,andforcealloutputstoalowstate,beforeastableclockhasbeen
applied. Withinputsheldlowandastableclockapplied,outputswillremain
low during the Low-to-High transition of RESET.
APPLICATIONS:
Ideally suited for stacked DIMM DDR registered applications
Along with CSPT857C/D, Zero Delay PLL Clock buffer, provides
complete solution for DDR1 DIMMs
FEATURES:
1:2 registered output buffer
2.3V to 2.7V operation for PC1600, PC2100, and PC2700
2.5V to 2.7V operation for PC3200
Single bit propagation delay, TSSOP : 2.2ns, VFQFPN : 1.8ns
SSTL_2 Class I style data inputs/outputs
Differential CLK input
RESET control compatible with LVCMOS levels
Latch-up performance exceeds 100mA
ESD >2000V per MIL-STD-883, Method 3015; >200V using
machine model (C = 200pF, R = 0)
Available in 56 pin VFQFPN and 64 pin TSSOP packages
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
51
48
49
45
35
R
1D
C1
16
Q1A
RESET
CLK
VREF
D1
TO 12 OTHER CHANNELS
32
Q1B
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