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參數資料
| 型號： | IDT79RC3610033MS |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 33 MHz, RISC MICROCONTROLLER, PQFP208 |
| 封裝： | CAVITY-DOWN, MQUAD-208 |
| 文件頁數： | 1/20頁 |
| 文件大?。?/td> | 593K |
| 代理商： | IDT79RC3610033MS |
1998 Integrated Device Technology, Inc.
x Instruction set compatible with the RISCore32 family of
CPUs
x System-level integration minimizes system cost
-
32-bit RISC CPU
-
4KB instruction cache on-chip
-
1KB data cache on-chip
-
Memory, DMA and I/O controllers
-
System peripherals
x 24 MIPS/ 42K Dhrystone-2.1 at 25 MHz
x 31 MIPS/ 55K Dhrystone-2.1 at 33 MHz
x Improved cache control and cache locking
x Flexible bus interface allows simple, low cost designs
-
De-multiplexed address and data bus
-
On-chip 4-deep Read/Write buffer
-
Programmable bus width (8-,16-, and 32-bit)
x On-chip DRAM controller with Address Multiplexer
-
Supports optional interleaved DRAMs
x On-chip memory and I/O controller
-
Chip selects, wait-state generator
-
Supports optional interleaved ROMs
-
Supports PCMCIA Master protocol
x On-chip DMA controller
-
4 internal channels, 2 external channels
x On-chip serial ports, timers, interrupt controller
x On-chip bi-directional IEEE 1284 Centronics Parallel
Port interface
x Built-in debug/emulator support
x MQUAD-208 packaging
CoProcessor
CPU
Integer
Core
4 KB I
Cache
1 KB D
Cache
Serial Com. Ctrl
Interrupt Ctrl
DMA Channels
Bidrectional
Centronics
PIO
4 deep Rd/Wr
Buffer
DRAM
Ctrl
Memory
Ctrl
I/O Ctrl
Wait-State
generation
32-bit Virtual
Address bus
32-bit
data bus
32-bit
Physical
Address bus
On
-c
hi
pI
/O
BIU