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參數(shù)資料
| 型號： | IDT9DB801CGLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48 |
| 文件頁數(shù)： | 1/20頁 |
| 文件大?。?/td> | 277K |
| 代理商： | IDT9DB801CGLFT |
Integrated
Circuit
Systems, Inc.
ICS9DB801
1015B—09/07/06
Pin Configurations
Recommended Application:
DB800 Version 2.0 Yellow Cover part with PCI Express
suppor with extended bypass mode frequency range.
Output Features:
8 - 0.7V current-mode differential output pairs
Supports zero delay buffer mode and fanout mode
Bandwidth programming available
Key Specifications:
Outputs cycle-cycle jitter < 50ps
Outputs skew: 50ps
50 - 200MHz operation
Extended frequency range in bypass mode:
Revision B: up tp 333.33 MHz
Revision C: up to 400 MHz
Features/Benefits:
Spread spectrum modulation tolerant, 0 to -0.5% down
spread and +/- 0.25% center spread.
Supports undriven differential outputs in PD# and
SRC_STOP# modes for power management.
Supports polarity inversion to the output enables ,
SRC_STOP and PD.
Eight Output Differential Buffer for PCI Express (50-200MHz)
48-pin SSOP & TSSOP
SRC_DIV#
1
48 VDDA
VDD
2
47 GNDA
GND
3
46 IREF
SRC_IN
4
45 LOCK
SRC_IN#
5
44 OE_7
OE_0
6
43 OE_4
OE_3
742 DIF_7
DIF_0
841 DIF_7#
DIF_0#
940 OE_INV
GND 10
39 VDD
VDD 11
38 DIF_6
DIF_1 12
37 DIF_6#
DIF_1# 13
36 OE_6
OE_1 14
35 OE_5
OE_2 15
34 DIF_5
DIF_2 16
33 DIF_5#
DIF_2# 17
32 GND
GND 18
31 VDD
VDD 19
30 DIF_4
DIF_3 20
29 DIF_4#
DIF_3# 21
28 HIGH_BW#
BYPASS#/PLL 22
27 SRC_STOP#
SCLK 23
26 PD#
SDATA 24
25 GND
OE_INV = 0
IC
S9
DB8
01
(S
am
e
as
IC
S
9
D
B
1
0
8
)
SRC_DIV#
1
48 VDDA
VDD
2
47 GNDA
GND
3
46 IREF
SRC_IN
4
45 LOCK
SRC_IN#
5
44 OE7#
OE0#
643 OE4#
OE3#
742 DIF_7
DIF_0
841 DIF_7#
DIF_0#
940 OE_INV
GND 10
39 VDD
VDD 11
38 DIF_6
DIF_1 12
37 DIF_6#
DIF_1# 13
36 OE6#
OE1# 14
35 OE5#
OE2# 15
34 DIF_5
DIF_2 16
33 DIF_5#
DIF_2# 17
32 GND
GND 18
31 VDD
VDD 19
30 DIF_4
DIF_3 20
29 DIF_4#
DIF_3# 21
28 HIGH_BW#
BYPASS#/PLL 22
27 SRC_STOP
SCLK 23
26 PD
SDATA 24
25 GND
OE_INV = 1
IC
S9
DB8
01
01
6OE_0
OE0#
7OE_3
OE3#
14
OE_1
OE1#
15
OE_2
OE2#
26
PD#
PD
27
SRC_STOP#
SRC_STOP
35
OE_5
OE5#
36
OE_6
OE6#
43
OE_4
OE4#
44
OE_7
OE7#
Polarity Inversion Pin List Table
Pins
OE_INV
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