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參數(shù)資料
| 型號(hào)： | IDTCSP2510DPGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER |
| 中文描述： | 2510 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封裝： | TSSOP-24 |
| 文件頁(yè)數(shù)： | 1/9頁(yè) |
| 文件大小： | 72K |
| 代理商： | IDTCSP2510DPGI |
1
0
°
C TO 85
°
C TEMPERATURE RANGE
IDTCSP2510D
3.3V PHASE-LOCK LOOP CLOCK DRIVER
OCT OBER 2001
2001 Integrated Device Technology, Inc.
DSC-5874/2
c
IDTCSP2510D
0oC T O 85oC T EMPERAT URE RANGE
3.3V PHASE-LOCK LOOP
CLOCK DRIVER
ZERO DELAY BUFFER
DE S CRIPT ION:
The CSP2510D is a high performance, low-skew, low-jitter, phase-lock
loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency
and phase, the feedback (FBOUT) output to the clock (CLK) input signal.
It is specifically designed for use with synchronous DRAMs. The CSP2510D
operates at 3.3V.
One bank of ten outputs provide low-skew, low-jitter copies of CLK.
Output signal duty cycles are adjusted to 50 percent, independent of the duty
cycle at CLK. The outputs can be enabled or disabled via the control G input.
When the G input is high, the outputs switch in phase and frequency with
CLK; when the G input is low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CSP2510D does not require
external RC networks. The loop filter for the PLL is included on-chip,
mnimzing component count, board space, and cost.
Because it is based on PLL circuitry, the CSP2510D requires a
stabilization time to achieve phase lock of the feedback signal to the
reference signal. This stabilization time is required, following power up and
application of a fixed-frequency, fixed-phase signal at CLK, as well as
following any changes to the PLL reference or feedback signals. The PLL
can be bypassed for the test purposes by strapping AV
DD
to ground.
The CSP2510D is specified for operation from0°C to +85°C. This device
is also available (on special order) in Industrial temperature range (-40°C
to +85°C). See ordering information for details.
21
Y9
PLL
3
5
8
9
4
Y0
Y1
Y2
Y3
Y4
15
17
20
16
Y5
Y6
Y7
Y8
24
13
23
AV
DD
FBIN
CLK
G
11
12
FBOUT
FUNCTIONAL BLOCK DIAGRAM
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
Phase-Lock Loop Clock Distribution for Synchronous DRAM
Applications
Distributes one clock input to one bank of ten outputs
Output enable bank control
External feedback (FBIN) pin is used to synchronize the
outputs to the clock input signal
No external RC network required for PLL loop stability
Operates at 3.3V V
DD
tpd Phase Error at 166MHz: < ±150ps
Jitter (peak-to-peak) at 166MHz: < ±75ps @ 166MHz
Spread Spectrum Compatible
Operating frequency 50MHz to 175MHz
Available in 24-Pin TSSOP package
APPLICATIONS:
SDRAMModules
PC Motherboards
Workstations
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDTCSP2510DPG | SENSOR OPTICAL SLOTTED 1.0MM |
| IDTCSP2510D | 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER |
| IDTCSPT857CNL | 2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPT857C | 2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPT857CBV | 2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDTCSP2510DPGI8 | 功能描述:IC CLK DVR PLL ZDB 1:10 24TSSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無(wú) 頻率 - 最大:240MHz 除法器/乘法器:是/無(wú) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| IDTCSP5940Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Ten Distributed-Output Clock Driver |
| IDTCSPF2510C | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V PHASE-LOCK LOOP CLOCK DRIVER |
| IDTCSPF2510CPG | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V PHASE-LOCK LOOP CLOCK DRIVER |
| IDTCSPF2510CPGG | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V PHASE-LOCK LOOP CLOCK DRIVER |
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