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參數(shù)資料
| 型號： | IDTCSPUA877ANLG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| 中文描述： | CSPUA877 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC40 |
| 封裝： | GREEN, PLASTIC, VFQFPN-40 |
| 文件頁數(shù)： | 1/14頁 |
| 文件大小： | 127K |
| 代理商： | IDTCSPUA877ANLG |
1
IDTCSPUA877A
1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
2006 Integrated Device Technology, Inc.
DSC 6872/4
c
IDTCSPUA877A
COMME RCIAL T E MPE RAT URE RANGE
1.8V PHASE LOCKED LOOP
DIFFERENTIAL 1:10 SDRAM
CLOCK DRIVER
OCT OBER 2006
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
1 to 10 differential clock distribution
Optimized for clock distribution in DDR2 (Double Data Rate)
SDRAMapplications
Operating frequency: 125MHz to 410MHz
Stabilization time: <6us
Very low skew:
≤
40ps
Very low jitter:
≤
40ps
1.8V AV
DD
and 1.8V V
DDQ
CMOS control signal input
Test mode enables buffers while disabling PLL
Low current power-down mode
Tolerant of Spread Spectrum input clock
Available in 52-Ball VFBGA and 40-pin VFQFPN packages
FUNCTIONAL BLOCK DIAGRAM
NOTE:
The Logic Detect (LD) powers down the device when a logic LOW is applied to both CLK and
CLK
.
DESCRIPTION:
The CSPUA877A is a PLL based clock driver that acts as a zero delay buffer
to distribute one differential clock input pair(CLK,
CLK
) to 10 differential
output pairs (Y
[0:9]
,
Y
[0:9]
) and one differential pair of feedback clock output
(FBOUT,
FBOUT
). External feedback pins (FBIN,
FBIN
) for synchronization
of the outputs to the input reference is provided. OE, OS, and A
VDD
control the
power-down and test mode logic. When A
VDD
is grounded, the PLL is turned
off and bypassed for test mode purposes. When the differential clock inputs
(CLK,
CLK
) are both at logic low, this device will enter a low power-down mode.
In this mode, the receivers are disabled, the PLL is turned off, and the output
clock drivers are disabled, resulting in a clock driver current consumption of less
than 500
μ
A.
The CSPUA877A requires no external components and has been optimsed
for very low phase error, skew, and jitter, while maintaining frequency and duty
cycle over the operating voltage and temperature range. The CSPUA877 ,
designed for use in both module assemblies and systemmotherboard based
solutions, provides an optimumhigh-performance clock source.
The CSPUA877A is available in Commercial Temperature Range (0
°
C to
+70
°
C). See Ordering Information for details.
APPLICATIONS:
Meets or exceeds JEDEC standard CUA877 for registered DDR2
clock driver
Along with SSTUA32864/66, DDR2 register, provides complete
solution for DDR2 DIMMs
Y0
Y0
FBOUT
Y1
Y1
Y5
Y5
Y4
Y4
Y3
Y3
Y2
Y2
Y8
Y8
Y6
Y6
Y7
Y7
Y9
Y9
FBOUT
FBIN
FBIN
PLL
CLK
CLK
POWER
DOWN
AND
TEST
MODE
LOGIC
LD
AV
DD
OE
OS
LD or OE
LD, OS, or OE
PLL BYPASS
10K
Ω
- 100K
Ω
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