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參數資料
| 型號： | IDTRC5000-250BS |
| 廠商： | Integrated Device Technology, Inc. |
| 元件分類： | 64位微處理器 |
| 英文描述： | MULTI-ISSUE 64-BIT MICROPROCESSOR |
| 中文描述： | 多發行64位微處理器 |
| 文件頁數： | 1/16頁 |
| 文件大小： | 298K |
| 代理商： | IDTRC5000-250BS |
1998 Integrated Device Technology, Inc.
1
COMMERCIAL TEMPERATURE RANGE
Integrated Device Technology, Inc.
FEATURES
Dual issue super-scalar execution core, executing at
high-frequency
- 250 MHz frequency
- Dual issue floating-point ALU operations with other
instruction classes
- Traditional 5-stage pipeline, minimizes load and
branch latencies
- Single cycle repeat rate for most floating point ALU
operations
High level of performance for a variety of applications
- High-performance 64-bit integer unit achieves 330
dhrystone MIPS (dhrystone 2.1)
- Ultra high-performance floating-point accelerator,
directly implementing single- and double-precision
operations achieves 500mflops
- Extremely large on-chip primary caches
- On-chip secondary cache controller
Large, efficient on-chip caches
- 32KB Instruction Cache, 32KB Data Cache
- 2-set associative in each cache
- Virtually indexed and physically tagged to minimize
cache flushes
- Write-back and write-through selectable on a per
page basis
- Critical word first cache miss processing
- Supports back-to-back loads and stores in any com-
bination at full pipeline rate
High-performance memory system
- Large primary caches integrated on-chip
- Secondary cache control interface on-chip
- High-frequency 64-bit bus interface runs up to
100MHz
- Aggregate bandwidth of on-chip caches, system
interface of 5GB/s
- High-performance write protocols for graphics and
data communications
MIPS-IV 64-bit ISA for improved computation
- Compound floating-point operations for 3D graphics
and floating-point DSP
- Conditional move operations
Compatible with a variety of operating systems
- Windows CE
- Numerous MIPS-compatible real-time operating sys-
tems
Uses input system clock, with processor pipeline
clock multiplied by a factor of 2-8
Large on-chip TLB
Active power management, including use of WAIT
operation
MULTI-ISSUE
64-BIT MICROPROCESSOR
June, 1998
BLOCK DIAGRAM
The IDT logo is a registered trademark and ORION, R4600, R4640, R4650, R4700, R5000, RV5000, and RISController are trademarks of Integrated Device Technology, Inc. MIPS is a registered
trademark of MIPS Computer Systems, Inc.
Instruction Tag B
ITLB Physical
Write Buffer
Read Buffer
DVA
IVA
F
I
DBus
Tag
AuxTag
IntIBus
FPIBus
ABus
Data Set A
Store Buffer
Phase Lock Loop
Data Tag A
DTLB Physical
Instruction Set A
Instruction Select
Integer Instruction Register
FP Instruction Register
Data Set B
Address Buffer
Instruction Tag A
SysAD
Control
Floating Point Register File
Unpacker/Packer
Joint TLB
Coprocessor 0
SystControl
PC Incrementer
Branch Adder
Instruction TLB Virtual
Program Counter
Load Aligner
Integer Register File
Integer/Address Adder
Data TLB Virtual
Shifter/Store Aligner
Logic Unit
Integer Multiply, Divide
MFDiv, SqRt
Instruction Set B
IDT RC5000
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