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參數資料
| 型號： | IMIB9948 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數： | 1/7頁 |
| 文件大小： | 39K |
| 代理商： | IMIB9948 |
B9940L
2.5V / 3.3V, 200 MHz, 1:18 Clock Distribution Buffer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07105 Rev. **
5/24/2001
Page 1 of 7
Product Features
200MHz Clock Support
LVPECL or LVCMOS/LVTTL Clock Input
LVCMOS/LVTTL Compatible Inputs
18 Clock Outputs: Drive up to 36 Clock Lines
150ps Maximum Output-to-Output Skew
Dual or Single Supply Operation:
3.3V Core and 3.3V Outputs
3.3V Core and 2.5V Outputs
2.5V Core and 2.5V Outputs
Pin Compatible with MPC940L
Industrial Temp. Range: -40°C to +85°C
32-Pin LQFP Package
Block Diagram
Figure 1
Description
The B9940L is a low voltage clock distribution buffer
with the capability to select either a differential LVPECL
or a LVCMOS/LVTTL compatible input clock. The two
clock sources can be used to provide for a test clock as
well as the primary system clock. All other control inputs
are LVCMOS/LVTTL compatible. The eighteen outputs
are 2.5V or 3.3V compatible and can drive two series
terminated 50
transmission lines. With this capability
the B9940L has an effective fan-out of 1:36. Low
output-to-output skews make the B9940L an ideal clock
distribution buffer for nested clock trees in the most
demanding of synchronous systems.
Pin Configuration
B9940L
Q
Q
Q
V
Q
Q
Q
V
Q
Q
Q
V
Q
Q
Q
V
Q6
Q7
Q8
VDD
Q9
Q10
Q11
VSS
VSS
VSS
TCLK
TCLK_SEL
PECL_CLK
PECL_CLK#
VDD
VDDC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
1
1
1
1
1
1
1
3
3
3
2
2
2
2
2
PECL_CLK
PECL_CLK#
0
1
TCLK
TCLK_SEL
VDDC
18
Q0-Q17
VDD
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