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參數資料
| 型號： | IMIZ9974 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數： | 1/9頁 |
| 文件大小： | 50K |
| 代理商： | IMIZ9974 |
3.3V, 180MHz, Multi-Output Zero Delay Buffer
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07084 Rev. *B
12/22/2002
Page 1 of 9
Z9951
Product Features
180MHz Clock Support
Supports PowerPC
TM
, Intel and RISC Processors
9 Clock Outputs: Frequency Configurable
Two Reference Clock Inputs for Dynamic Toggling
Oscillator or PECL Reference Input
Output Disable Control
Spread Spectrum Compatible
3.3V Power Supply
Pin Compatible with MPC951
Industrial Temp. Range: -40°C to +85°C
32-Pin TQFP Package
Block Diagram
Figure 1
Frequency Table
SEL (A:D)
QA
QB
QC (0,1)
QD (0:4)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
VCO/2
VCO/2
VCO/2
VCO/2
VCO/2
VCO/2
VCO/2
VCO/2
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/8
VCO/8
VCO/8
VCO/8
VCO/4
VCO/4
VCO/4
VCO/4
VCO/8
VCO/8
VCO/8
VCO/8
Table 1
VCO/4
VCO/4
VCO/8
VCO/8
VCO/4
VCO/4
VCO/8
VCO/8
VCO/4
VCO/4
VCO/8
VCO/8
VCO/4
VCO/4
VCO/8
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
Pin Configuration
Z9951
R
P
T
V
Q
V
Q
V
P
M
V
Q
V
Q
V
Q
QC0
VDDC
QC1
VSS
QD0
VDDC
QD1
VSS
VDD
FB_IN
SELA
SELB
SELC
SELD
VSS
PECL_CLK
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
1
1
1
1
1
1
1
3
3
3
2
2
2
2
2
Phase
Detector
VCO
200-
480MHz
LPF
2/ 4
4/ 8
4/ 8
4/ 8
QA
QB
QC0
QC1
QD0
QD1
QD2
QD3
QD4
SELA
PLL_EN
TCLK
REF_SEL
PECL_CLK
PECL_CLK#
FB_IN
SELB
SELC
MR/OE#
Power-On Reset
SELD
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