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參數資料
| 型號： | IOP480 |
| 英文描述： | I/O Processor|IOP 480 Design Notes |
| 中文描述： | I / O處理器|眼壓480設計說明 |
| 文件頁數： | 1/11頁 |
| 文件大小： | 245K |
| 代理商： | IOP480 |
;
IOP 480 AA
Design Note Rev. 1.3
March 2002
Design Note Documentation
A.
This document details Design Notes for the following silicon:
Product
Part Number
Affected Silicon Revision
Description
60MHz Local Bus
208-pin PQFP Product
66MHz Local Bus
208-pin PQFP Product
60MHz Local Bus
225-pin PBGA Product
66MHz Local Bus
225-pin PBGA Product
Status
IOP 480 AA
IOP480-AA60PI
In production October 1999
IOP 480 AA
IOP480-AA66PI
In production October 1999
IOP 480 AA
IOP480-AA60BI
In production October 1999
IOP 480 AA
IOP480-AA66BI
In production October 1999
B.
The following documentation is the baseline functional description of the silicon.
Errata are defined as behaviors in the affected silicon that do not match
behaviors detailed in this documentation.
Document
Revision
IOP 480 Data Book
See www.plxtech.com
C. Design Note Summary
#
Description
1
End-of-Transfer (EOT) During Chaining DMA End Link Mode with Write-back
2
DMA Channel 2 with End-of-Transfer (EOTx#) asserted coincident with ADS#
3
Zero Wait State SRAM Writes
External local master write to IOP 480 internal configuration registers with WAIT# being used
to insert wait states
5
Modifying internal configuration registers that affect on-going transfers
6
Operation of IOP 480 Buffers in 3.3 Volt Signaling Environment
7
LCSx# Chip Select output delayed when IOP 480 is initiating access to SRAM
8
CompactPCI Hot Swap Insertion Bit Status
9
DMPAF# (Direct Master Programmable Almost Full) negation timing
Messaging Unit data corruption if Queue Prefetch (Inbound Free List FIFO Prefetch and/or
Outbound Post List FIFO Prefetch) is enabled
11
Local Bus Timeout with SDRAM
12
WAIT# input signal when using the Memory Controller
Documentation Status
Description
Released Data Book
IOP 480 Errata
Documentation
Publication Date
July 2000
IOP 480 AA Errata
4
10
Confidential
Document number: DN-IOP 480 Rev AA-SIL-1.3
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