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參數資料
| 型號： | IRPT4052 |
| 文件頁數： | 12/12頁 |
| 文件大小： | 174K |
| 代理商： | IRPT4052 |
page 12
IRPT 4052
WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331
EUROPEAN HEADQUARTERS:
Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020
IR CANADA:
7321 Victoria Park Ave., Suite 201, Markham, Ontario L3R 2Z8, Tel: (905) 475 1897
IR GERMANY:
Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590
IR ITALY:
Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111
IR FAR EAST:
171 (K&H Bldg.), 3-30-4 Nishi-ikebukuro 3-Chome, Toshima-ku, Tokyo Japan Tel: 81 3 3983 0086
IR SOUTHEAST ASIA:
315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 0316 Tel: 65 221 8371
http://www.irf.com/
Data and specifications subject to change without notice.
3/97
Undervoltage (Local Power Supply)
The undervoltage circuit monitors the voltage of the local gate
driver power supply and sends a high input signal during
undervoltage which sets the latch and inhibits the PWM input
signals. This signal, brought out on pin 18 of CN5, is high during
undervoltage. After it has gone low during power-up, a 15V RE-
SET signal must be applied to reset the latch and allow the PWM
input signals to pass to the gate drive circuits.
Overcurrent Trip
Peak line-to-line fault current in excess of a nominal value of
45A and peak line-to-ground current in excess of 40A sets the
latch and internally inhibits the IGBT gate drive. The overcurrent
feedback signal, OI, simultaneously goes high. Reaction time to
a bolted short circuit is typically about 1μsec.
Overtemperature Trip
If the temperature of the IMS substrate exceeds a nominal
value of 100°C, the overtemperature circuit sets the latch and
internally inhibits the PWM input signals. The overtemperature
feedback signal, OT, simultaneously goes high.
Latch Reset
The LED1 lights up when any of the fault signals (UV, OI,
OT) set the latch, indicating a fault condition. When the RESET
signal is applied to the latch, the LED1 goes OFF if the fault that
is setting the latch clears.
The internal PWM inhibit condition is cleared by applying a
15V signal to the RESET terminal for a minimum period of
1 microsecond
Heat Sink Requirements
Figures 5a through 5d (pp. 6-7) show the thermal resistance of
the heat sink required for various output power levels and PWM
switching frequencies. Maximum total losses of the unit are also
shown.
This data is based on the following key operating conditions:
The maximum continuous combined losses of the rectifier
and inverter occur at full pulse-width modulation. These
maximum losses set the maximum continuous operating
temperature of the heat sink.
The maximum combined losses of the rectifier and inverter
at full pulse-width modulation under overload set the incre-
mental temperature rise of the heat sink during overload.
The minimum output frequency at which full overload cur-
rent is to be delivered sets the peak IGBT junction
temperatures.
At low frequency IGBT junction temperature tends to follow
the instantaneous fluctuations of the output current. Thus, peak
junction temperature rise increases as output frequency de-
creases.
Voltage Rise During Braking
The motor will feed energy back to the DC link during electri-
cal braking, forcing the DC bus voltage to rise above the level
defined by the input line voltage.
Deceleration of the motor must be controlled by appropriate
PWM control to keep the DC bus voltage within the rated maxi-
mum value. For high inertial loads or for very fast deceleration
rates, this can be achieved by connecting an external dissipative
circuit, which keeps the bus voltage within the rated value across
the P and N.
J
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