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參數資料
型號: IRS2548DSPBF
廠商: International Rectifier
文件頁數: 13/22頁
文件大?。?/td> 320K
描述: IC PFC
特色產品: IRS2548D LED Driver
標準包裝: 55
系列: *
 
IRS2548D
 
 
www.irf.com
?2011 International Rectifier
13
Application Information and Additional
Details
 
I. LED Driver Section
Functional Description
 
Under-voltage Lock-Out Mode (UVLO)
 
The under-voltage lock-out mode (UVLO) is defined
as the state the IC is in when VCC is below the
turn-on   threshold   of   the   IC.   The   IRS2548D
undervoltage lock-out is designed to maintain an
ultra low supply current and to guarantee the IC is
fully functional before the high and low-side output
drivers and PFC are activated. Figure 1 shows a
possible VCC supply voltage scheme using the
micro-power start-up current of the IRS2548D
together with a snubber charge pump from the half-
bridge output (R
VCC
, C
VCC1
, C
VCC2
,
 
C
SNUB
,
 
D
CP1
 and
D
CP2
).
 
IRS2548D
LO
COM
VB
VS
HO
V
BUS
(+)
V
BUS
(-)
VCC
C
BS
14
MHS
C
VCC2
R
VCC
D
CP1
D
CP2
To Load
R
CS
C
SNUB
MLS
13
12
11
10
9
V
RECT
(+)
C
VCC1
CS
8
R
3
C
CS
IC
COM
Load
Return
R
1
R
2
R
LO
R
HO
BSFET
CONTROL
BSFET
 
 
Figure 1:  Start-up and supply circuitry. 
 
The VCC capacitors (C
VCC1
 and C
VCC2
) are charged
by the current through supply resistor (R
VCC
) minus
the start-up current drawn by the IC. This resistor is
chosen to set the desired AC line input voltage turn-
on threshold for the system. When the voltage at
VCC exceeds the IC start-up threshold (VCCUV+)
and the ENN pin is below 1.5 volts, the IC turns on
and LO begins to oscillate. The capacitors at VCC
begin to discharge due to the increase in IC
operating current (Figure 2). The high-side supply
voltage, VB-VS, begins to increase as capacitor
C
BS
is charged through the internal bootstrap
MOSFET during the LO on-time of each LO
switching cycle. When the VB-VS voltage exceeds
the high-side start-up threshold (VBSUV+), HO
then begins to oscillate. This may take several
cycles of LO to charge VB-VS above VBSUV+ due
to RDSon of the internal bootstrap MOSFET.
DISCHARGE
TIME
INTERNAL VCC
ZENER CLAMP VOLTAGE
VHYST
V
UVLO+
V
UVLO-
CHARGE PUMP
OUTPUT
t
V
C1
R
VCC
 & C
VCC1,2
TIME
CONSTANT
C
VCC
DISCHARGE
 
   
Figure 2:  VCC supply voltage. 
 
When LO and HO are both oscillating, the external
MOSFETs (MHS and MLS) are turned on and off with
a 50% duty cycle and a non-overlapping deadtime of
1.6us. The half-bridge output (pin VS) begins to
switch between the DC bus voltage and COM. During
the deadtime between the turn-off of LO and the turn-
on of HO, the half-bridge output voltage transitions
from COM to the DC bus voltage at a dv/dt rate
determined by the snubber capacitor (C
SNUB
). As the
snubber capacitor charges, current will flow through
the charge pump diode (D
CP2
) to VCC. After several
switching cycles of the half-bridge output, the charge
pump and the internal 15.6V zener clamp of the IC
take over as the supply voltage. Capacitor C
VCC2
supplies the IC current during the VCC discharge
time and should be large enough such that VCC does
not decrease below UVLO- before the charge pump
takes over.
This   scheme   can   be   used   in   non-dimming
applications, however where PWM dimming is used
the charge pump may not supply enough current to
VCC at low dimming levels and in this case an
auxiliary power supply is required.
Capacitor C
VCC1
is required for noise filtering and
must be placed as close as possible and directly
between VCC and COM, and should not be lower
than 0.1uF. Resistors R
1
  and R
2
are recommended
for limiting high currents that can flow to VCC from
the charge pump. The internal bootstrap MOSFET
and supply capacitor (C
BS
) provide the floating supply
voltage for the high side driver circuitry. During
UVLO mode the high and low-side driver outputs HO
and LO are both low and the internal oscillator is
disabled. 
 
 
 
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