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參數資料
| 型號： | IS32WV10008ALL-85BI |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | SRAM |
| 英文描述： | 1M X 8 PSEUDO STATIC RAM, 85 ns, PBGA48 |
| 封裝： | 6 X 8 MM, BGA-48 |
| 文件頁數： | 1/12頁 |
| 文件大小： | 53K |
| 代理商： | IS32WV10008ALL-85BI |
IS32WV10008ALL
IS32WV10008BLL
ISSI
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
1
Rev. 00A
08/15/02
Copyright 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice.
ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
1Meg x 8 LOW VOLTAGE,
ULTRA LOW POWER PSEUDO RAM
FEATURES
High-speed access time: 55ns, 70, 85, 100ns
CMOS low power operation
TTL compatible interface levels
Single power supply
– 1.65V--2.2V VDD (32WV10008ALL)
– 2.3V--3.6V VDD (32WV10008BLL)
Fully static operation: no clock or refresh
required
Three state outputs
Industrial temperature available
DESCRIPTION
The
ISSI IS32WV10008ALL/ IS32WV10008BLL are high-
speed, 8M bit static RAMs organized as 1M words by 8 bits.
It is fabricated using
ISSI's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields high-
performance and low power consumption devices.
When
CS1 is HIGH (deselected) or when CS2 is LOW
(deselected) or when
CS1 is LOW, CS2 is HIGH, the device
assumes a standby mode at which the power dissipation
can be reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE) controls both writing and reading of the memory.
The IS32WV10008ALL and IS32WV10008BLL are packged
in the JEDEC standard 48-pin mini BGA (6mm x 8mm) and
44-Pin TSOP (TYPE II).
FUNCTIONAL BLOCK DIAGRAM
ADVANCED INFORMATION
AUGUST 2002
A0-A19
CS1
OE
WE
1M x 8
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VDD
I/O
DATA
CIRCUIT
DQ0-DQ7
CS2
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