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參數資料
| 型號： | IS41C16256-35T |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| 中文描述： | 256K X 16 EDO DRAM, 35 ns, PDSO40 |
| 封裝： | 0.400 INCH, MS-24, TSOP2-40/44 |
| 文件頁數： | 6/20頁 |
| 文件大?。?/td> | 215K |
| 代理商： | IS41C16256-35T |
IS41C16256
IS41LV16256
6
Integrated Circuit Solution Inc.
DR001-0E 01/25/2002
ELECTRICAL CHARACTERISTICS
(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol
Parameter
Test Condition
Speed
Min.
Max.
Unit
I
IL
Input Leakage Current
Any input 0V < V
IN
< Vcc
Other inputs not under test = 0V
–10
10
μA
I
IO
Output Leakage Current
Output is disabled (Hi-Z)
0V < V
OUT
< Vcc
–10
10
μA
V
OH
Output High Voltage Level
I
OH
= –2.5 mA
2.4
—
V
V
OL
Output Low Voltage Level
I
OL
=+2.1mA
—
0.4
V
I
CC
1
Standby Current: TTL
RAS
,
LCAS
,
UCAS
> V
IH
Commerical
Industrial
Commerical 3.3V
Industrial
5V
5V
—
—
—
—
2
3
1
2
mA
3.3V
I
CC
2
Standby Current: CMOS
RAS
,
LCAS
,
UCAS
> V
CC
– 0.2V
5V
3.3V
—
—
1
mA
0.5
I
CC
3
Operating Current:
Random Read/Write
(2,3,4)
Average Power Supply Current
RAS
,
LCAS
,
UCAS
,
Address Cycling, t
RC
= t
RC
(min.)
-25
-35
-50
-60
—
—
—
—
260
230
180
170
mA
I
CC
4
Operating Current:
EDO Page Mode
(2,3,4)
Average Power Supply Current
RAS
= V
IL
,
LCAS
,
UCAS
,
Cycling t
PC
= t
PC
(min.)
-25
-35
-50
-60
—
—
—
—
250
220
170
160
mA
I
CC
5
Refresh Current:
RAS
-Only
(2,3)
Average Power Supply Current
RAS
Cycling,
LCAS
,
UCAS
> V
IH
t
RC
= t
RC
(min.)
-25
-35
-50
-60
—
—
—
—
260
230
180
170
mA
I
CC
6
Refresh Current:
CBR
(2,3,5)
Average Power Supply Current
RAS
,
LCAS
,
UCAS
Cycling
t
RC
= t
RC
(min.)
-25
-35
-50
-60
—
—
—
—
260
230
180
170
mA
Notes:
1. An initial pause of 200 μs is required after power-up followed by eight
RAS
refresh cycles (
RAS
-Only or CBR) before proper device
operation is assured. The eight
RAS
cycles wake-up should be repeated any time the t
REF
refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
相關PDF資料 |
PDF描述 |
|---|---|
| IS41C16256-50KI | 256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| IS41C16256-50TI | 256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| IS41C16256-60K | 256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| IS41C16256-60KI | 256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| IS41C16256-60T | 256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
相關代理商/技術參數 |
參數描述 |
|---|---|
| IS41C16256-35TI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| IS41C16256-40K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 EDO Page Mode DRAM |
| IS41C16256-40KI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 EDO Page Mode DRAM |
| IS41C16256-40T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 EDO Page Mode DRAM |
| IS41C16256-40TI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 EDO Page Mode DRAM |
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