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參數資料
| 型號： | IS41C44002A |
| 英文描述： | 4M x 4 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| 中文描述： | 4米× 4（16兆）動態與江戶頁面模式內存 |
| 文件頁數： | 4/20頁 |
| 文件大小： | 297K |
| 代理商： | IS41C44002A |
4
Integrated Circuit Solution Inc.
DR026-0A 09/04/2001
IC41C44002A/IC41C44002AS(L)
IC41LV44002A/IC41LV44002AS(L)
Functional Description
The IC41C44002A and IC41LV44002A are CMOS DRAMs
optimized for high-speed bandwidth, low power
applications. During READ or WRITE cycles, each bit is
uniquely addressed through the 11 address bits. These are
entered 11 bits (A0-A10) at a time for the 2K refresh device
. The row address is latched by the Row Address Strobe
(
RAS
). The column address is latched by the Column
Address Strobe (
CAS
).
RAS
is used to latch the first 11 bits
and
CAS
is used to latch the latter 11 bits.
Memory Cycle
A memory cycle is initiated by bring
RAS
LOW and it is
terminated by returning both
RAS
and
CAS
HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum t
RAS
time has expired. A new
cycle must not be initiated until the minimum precharge
time t
RP
, t
CP
has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of
CAS
or
OE
,
whichever occurs last, while holding
WE
HIGH. The
column address must be held for a minimum time specified
by t
AR
. Data Out becomes valid only when t
RAC
, t
AA
, t
CAC
and t
OE
are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.
Write Cycle
A write cycle is initiated by the falling edge of
CAS
and
WE
,
whichever occurs last. The input data must be valid at or
before the falling edge of
CAS
or
WE
, whichever occurs
last.
Refresh Cycle
To retain data, 2,048 refresh cycles are required in each
32 ms period. There are two ways to refresh the memory:
1. By clocking each of the 2,048 row addresses (A0
through A10) with
RAS
at least once every 32 ms. Any
read, write, read-modify-write or
RAS
-only cycle re-
freshes the addressed row.
2. Using a
CAS
-before-
RAS
refresh cycle.
CAS
-before-
RAS
refresh is activated by the falling edge of
RAS
,
while holding
CAS
LOW. In
CAS
-before-
RAS
refresh
cycle, an internal 11-bit counter provides the row ad-
dresses and the external address inputs are ignored.
CAS
-before-
RAS
is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Self Refresh Cycle
(1)
The Self Refresh allows the user a dynamic refresh, data
retention mode at the extended refresh period of 64 ms. i.
e., 32 μs per row when using distributed CBR refreshes.
The feature also allows the user the choice of a fully static,
low power data retention mode. The optional Self Refresh
feature is initiated by performing a CBR Refresh cycle and
holding
RAS
LOW for the specified t
RASS
.
The Self Refresh mode is terminated by driving
RAS
HIGH
for a minimum time of t
RPS
. This delay allows for the
completion of any internal refresh cycles that may be in
process at the time of the
RAS
LOW-to-HIGH transition. If
the DRAM controller uses a distributed refresh sequence,
a burst refresh is not required upon exiting Self Refresh.
However, if the DRAM controller utilizes a
RAS
-only or
burst refresh sequence, all 2048 rows must be refreshed
within the average internal refresh rate, prior to the resump-
tion of normal operation.
Power
-
On
After application of the V
CC
supply, an initial pause of
200 μs is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS
signal).
During power-on, it is recommended that
RAS
track with
V
CC
or be held at a valid V
IH
to avoid current surges.
Note:
1.Self Refresh is for S version only.
相關PDF資料 |
PDF描述 |
|---|---|
| IS41C44002AS(L) | 4M x 4 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| IS41LV44002A | 4M x 4 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| IS41LV44002AS(L) | 4M x 4 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| IS41C44002 | 4Mx4 bit Dynamic RAM with EDO Page Mode |
| IS41C44004 | 4Mx4 bit Dynamic RAM with EDO Page Mode |
相關代理商/技術參數 |
參數描述 |
|---|---|
| IS41C44002AS(L) | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:4M x 4 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| IS41C44002C | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:16Mb DRAM WITH EDO PAGE MODE |
| IS41C44004 | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:4M x 4 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| IS41C44004-50J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 EDO Page Mode DRAM |
| IS41C44004-50JI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:4M x 4 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
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