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參數資料
| 型號： | IS41LV16100S-50T |
| 英文描述： | 1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| 中文描述： | 100萬× 16（16兆）動態與江戶頁面模式內存 |
| 文件頁數： | 8/20頁 |
| 文件大?。?/td> | 533K |
| 代理商： | IS41LV16100S-50T |
IS41C16100S
IS41LV16100S
8
Integrated Circuit Solution Inc.
DR004-0B
AC CHARACTERISTICS
(Continued)
(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-45
-50
-60
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Units
t
ACH
Column-Address Setup Time to
CAS
15
—
15
—
15
—
ns
Precharge during WRITE Cycle
OE
Hold Time from
WE
during
READ-MODIFY-WRITE cycle
(18)
t
OEH
6
—
8
—
10
—
ns
t
DS
Data-In Setup Time
(15, 22)
0
—
0
—
0
—
ns
t
DH
Data-In Hold Time
(15, 22)
6
—
8
—
10
—
ns
t
RWC
READ-MODIFY-WRITE Cycle Time
RAS
to
WE
Delay Time during
READ-MODIFY-WRITE Cycle
(14)
CAS
to
WE
Delay Time
(14, 20)
Column-Address to
WE
Delay Time
(14)
95
—
108
—
133
—
ns
t
RWD
55
—
64
—
77
—
ns
t
CWD
21
—
26
—
32
—
ns
t
AWD
32
—
39
—
47
—
ns
t
PC
EDO Page Mode READ or WRITE
16
—
20
—
25
—
ns
Cycle Time
(24)
RAS
Pulse Width in EDO Page Mode
Access Time from
CAS
Precharge
(15)
t
RASP
45
100K
50
100K
60
100K
ns
t
CPA
—
27
—
30
—
35
ns
t
PRWC
EDO Page Mode READ-WRITE
51
—
56
—
68
—
ns
Cycle Time
(24)
Data Output Hold after
CAS
LOW
t
COH
5
—
5
—
5
—
ns
t
OFF
Output Buffer Turn-Off Delay from
CAS
or
RAS
(13,15,19, 29)
Output Disable Delay from
WE
Last
CAS
going LOW to First
CAS
returning HIGH
(23)
CAS
Setup Time (CBR REFRESH)
(30, 20)
CAS
Hold Time (CBR REFRESH)
(30, 21)
OE
Setup Time prior to
RAS
during
1.6
11
1.6
12
1.6
15
ns
t
WHZ
3
10
3
10
3
10
ns
t
CLCH
8
—
10
—
10
—
ns
t
CSR
5
—
5
—
5
—
ns
t
CHR
8
—
8
—
10
—
ns
t
ORD
0
—
0
—
0
—
ns
HIDDEN REFRESH Cycle
t
REF
Auto Refresh Period (1,024 Cycles)
—
16
—
16
—
16
ms
t
REF
Self Refresh Period (1,024 Cycles)
—
128
—
128
—
128
ms
t
T
Transition Time (Rise or Fall)
(2, 3)
1
50
1
50
1
50
ns
AC TEST CONDITIONS
Output load:
Two TTL Loads and 50 pF (Vcc = 5.0V ±10%)
One TTL Load and 50 pF (Vcc = 3.3V ±10%)
Input timing reference levels: V
IH
= 2.4V, V
IL
= 0.8V (Vcc = 5.0V ±10%);
V
IH
= 2.0V, V
IL
= 0.8V (Vcc = 3.3V ±10%)
Output timing reference levels: V
OH
= 2.0V, V
OL
= 0.8V (Vcc = 5V ±10%, 3.3V ±10%)
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| IS41LV16100S-60K | 1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| IS41LV16100S-60KI | 1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| IS41LV16100S-60T | 1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| IS41LV16100S-60TI | 1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
相關代理商/技術參數 |
參數描述 |
|---|---|
| IS41LV16100S-50TI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| IS41LV16100S-60K | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| IS41LV16100S-60KI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| IS41LV16100S-60T | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| IS41LV16100S-60TI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
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