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參數(shù)資料
| 型號： | IS42LS32400A-10B |
| 英文描述： | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| 中文描述： | 16Meg × 8，8Meg x16 |
| 文件頁數(shù)： | 9/66頁 |
| 文件大小： | 556K |
| 代理商： | IS42LS32400A-10B |
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Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
ADVANCED INFORMATION
Rev. 00A
06/01/02
9
ISSI
IS42S81600A, IS42S16800A, IS42S32400A
IS42LS81600A, IS42LS16800A, IS42LS32400A
GENERAL DESCRIPTION
READ
The READ command selects the bank from BA0, BA1
inputs and starts a burst read access to an active row.
Inputs A0-A7 provides the starting column location. When
A10 is HIGH, this command functions as an AUTO
PRECHARGE command. When the auto precharge is
selected, the row being accessed will be precharged at the
end of the READ burst. The row will remain open for
subsequent accesses when AUTO PRECHARGE is not
selected. DQ’s read data is subject to the logic level on the
DQM inputs two clocks earlier. When a given DQM signal
was registered HIGH, the corresponding DQ’s will be High-
Z two clocks later. DQ’s will provide valid data when the
DQM signal was registered LOW.
WRITE
A burst write access to an active row is initiated with the
WRITE command. BA0, BA1 inputs selects the bank, and
the starting column location is provided by inputs A0-A7.
Whether or not AUTO-PRECHARGE is used is determined
by A10.
The row being accessed will be precharged at the end of the
WRITE burst, if AUTO PRECHARGE is selected. If AUTO
PRECHARGE is not selected, the row will remain open for
subsequent accesses.
A memory array is written with corresponding input data on
DQ’s and DQM input logic level appearing at the same time.
Data will be written to memory when DQM signal is LOW.
When DQM is HIGH, the corresponding data inputs will be
ignored, and a WRITE will not be executed to that byte/
column location.
PRECHARGE
The PRECHARGE command is used to deactivate the open
row in a particular bank or the open row in all banks. BA0,
BA1 can be used to select which bank is precharged or they
are treated as “Don’t Care”. A10 determined whether one or
all banks are precharged. After executing this command,
the next command for the selected banks(s) is executed
after passage of the period t
, which is the period required
for bank precharging. Once a bank has been precharged,
it is in the idle state and must be activated prior to any READ
or WRITE commands being issued to that bank.
AUTO PRECHARGE
The AUTO PRECHARGE function ensures that the precharge
is initiated at the earliest valid stage within a burst. This
function allows for individual-bank precharge without requir-
ing an explicit command. A10 to enables the AUTO
PRECHARGE function in conjunction with a specific READ
or WRITE command. For each individual READ or WRITE
command, auto precharge is either enabled or disabled.
AUTO PRECHARGE does not apply except in full-page
burst mode. Upon completion of the READ or WRITE burst,
a precharge of the bank/row that is addressed is automati-
cally performed.
AUTO REFRESH COMMAND
This command executes the AUTO REFRESH operation.
The row address and bank to be refreshed are automatically
generated during this operation. The stipulated period (t
RC
) s
required for a single refresh operation, and no other com-
mands can be executed during this period. This command s
executed at least 4096 times for every 64ms. During an
AUTO REFRESH command, address bits are “Don’t Care”.
This command corresponds to CBR Auto-refresh.
BURST TERMINATE
The BURST TERMINATE command forcibly terminates the
burst read and write operations by truncating either fixed-
length or full-page bursts and the most recently registered
READ or WRITE command prior to the BURST TERMI-
NATE.
COMMAND INHIBIT
COMMAND INHIBIT prevents new commands from being
executed. Operations in progress are not affected, apart
from whether the CLK signal is enabled
NO OPERATION
When
CS
is low, the NOP command prevents unwanted
commands from being registered during idle or wait states.
LOAD MODE REGISTER
During the LOAD MODE REGISTER command the mode
register is loaded from A0-A11. This command can only be
issued when all banks are idle.
EXTENDED MODE REGISTER
The extended mode register defines low power functions.
During this command A0-A11 are data input pins. After
power on, the extended mode register set command must
be executed to fix low power functions. During tRSC
following this command, they can not accept any other
command.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS42LS32400A | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42LS32400A-10TI | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42LS32400A-7B | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42LS32400A-7BI | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42LS32400A-7T | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS42LS32400A-10BI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42LS32400A-10T | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42LS32400A-10TI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42LS32400A-7B | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42LS32400A-7BI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
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