- 您現在的位置：買賣IC網 > PDF目錄360984 > IS42S32400A-7BI 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM PDF資料下載
參數資料
| 型號： | IS42S32400A-7BI |
| 英文描述： | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| 中文描述： | 16Meg × 8，8Meg x16 |
| 文件頁數： | 56/66頁 |
| 文件大小： | 556K |
| 代理商： | IS42S32400A-7BI |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁當前第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁
ISSI
56
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
ADVANCED INFORMATION
Rev. 00A
06/01/02
IS42S81600A, IS42S16800A, IS42S32400A
IS42LS81600A, IS42LS16800A, IS42LS32400A
DON'T CARE
CLK
COMMAND
BANK n
BANK m
ADDRESS
DQ
T0
T1
T2
T3
T4
T5
T6
T7
NOP
NOP
NOP
NOP
NOP
NOP
D
IN
a
D
IN
a+1
D
OUT
b
D
OUT
b+1
BANK n,
COL a
BANK m,
COL b
CAS Latency - 3 (BANK m)
t
RP - BANK n
t
RP - BANK m
Precharge
WRITE - AP
BANK n
READ - AP
BANK m
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
t
WR
- BANK n
Precharge
Page Active
READ with Burst of 4
Internal States
DON'T CARE
CLK
COMMAND
BANK n
BANK m
ADDRESS
DQ
T0
T1
T2
T3
T4
T5
T6
T7
NOP
NOP
NOP
NOP
NOP
NOP
BANK n,
COL a
BANK m,
COL b
t
RP - BANK n
RP - BANK m
Write-Back
BANK n
WRITE - AP
BANK m
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
t
WR
- BANK n
Precharge
Page Active
WRITE with Burst of 4
Internal States
D
IN
a
D
IN
a+1
D
IN
a+2
D
IN
b
D
IN
b+1
D
IN
b+2
D
IN
b+3
WRITE with Auto Precharge
3. Interrupted by a READ (with or without auto precharge):
A READ to bank m will interrupt a WRITE on bank n when
registered, with the data-out appearing
(CAS atency)
ater.
The PRECHARGE to bank n will begin after t
WR
is met,
where t
WR
begins when the READ to bank m is registered.
The ast valid
WRITE
to bank n will be data-in registered one
clock prior to the READ to bank m.
4. Interrupted by a WRITE (with or without auto precharge):
A
WRITE
to bank m will interrupt a
WRITE
on bank n when
registered. The PRECHARGE to bank n will begin after t
WR
is met, where t
WR
begins when the WRITE to bank m is
registered. The ast valid data WRITE to bank n will be data
registered one clock prior to a WRITE to bank m.
WRITE With Auto Precharge interrupted by a READ
WRITE With Auto Precharge interrupted by a WRITE
相關PDF資料 |
PDF描述 |
|---|---|
| IS42S32400A-7T | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S32400A-7TI | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42LS32400A-10B | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42LS32400A | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42LS32400A-10TI | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| IS42S32400A-7BL | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS42S32400A-7T | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S32400A-7TI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S32400A-7TL | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS42S32400A-7TLI | 制造商:Integrated Silicon Solution Inc 功能描述: |
發布緊急采購，3分鐘左右您將得到回復。