欧美成人免费电影,国产欧美一区二区三区精品酒店,精品国产a毛片,色网在线免费观看

參數資料
型號: IS42S32400A-7T
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM
中文描述: 4M X 32 SYNCHRONOUS DRAM, 5.4 ns, PDSO86
封裝: PLASTIC, TSOP2-86
文件頁數: 2/66頁
文件大?。?/td> 556K
代理商: IS42S32400A-7T
ISSI
2
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
ADVANCED INFORMATION
Rev. 00A
06/01/02
IS42S81600A, IS42S16800A, IS42S32400A
IS42LS81600A, IS42LS16800A, IS42LS32400A
DEVICE OVERVIEW
The 128Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in 2.5V V
DD
and 1.8V V
DDQ
or 3.3V
DD
and 3.3V V
DDQ
memory systems
containing 134,217 ,728 bits. Internally configured as a
quad-bank DRAM with a synchronous interface. Each
16,777,216-bit bank is organized as 4,096 rows by 256
columns by 16 bits.
The 128Mb SDRAM includes an AUTO REFRESH MODE,
and a power-saving, power-down mode. All signals are
registered on the positive edge of the clock signal, CLK. All
inputs and outputs are LVTTL compatible.
Only partials of the memory array can be selected for Self-
Refresh and the refresh period during Self-Refresh is
progammable in 4 steps which drastically reduces the self
refresh current, depending on the case temperature of the
components in the system application.
The 128Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during burst
access.
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE func-
tion enabled.
Precharge
one bank while accessing one of the
other three banks will hide the
precharge
cycles and provide
seamless, high-speed, random-access operation.
SDRAM
read and write accesses are burst oriented starting at
a selected location and continuing for a programmed num-
ber of locations in a programmed sequence. The registra-
tion of an ACTIVE command begins accesses, followed by
a READ or WRITE command. The ACTIVE command in
conjunction with address bits registered are used to select
the bank and row to be accessed (BA0, BA1 select the
bank; A0-A11 select the row). The READ or WRITE
commands in conjunction with address bits registered are
used to select the starting column location for the burst
access.
Programmable READ or WRITE burst lengths consist of 1,
2, 4 and 8 locations or full page, with a burst terminate
option.
CLK
CKE
CS
RAS
CAS
WE
A11
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
A10
COMMAND
DECODER
&
CLOCK
GENERATOR
MODE
REGISTER
REFRESH
CONTROLLER
REFRESH
COUNTER
SELF
REFRESH
CONTROLLER
ROW
ADDRESS
LATCH
M
COLUMN
ADDRESS LATCH
BURST COUNTER
COLUMN
ADDRESS BUFFER
COLUMN DECODER
DATA IN
BUFFER
DATA OUT
BUFFER
DQM
I/O 0-15
Vcc/Vcc
Q
GND/GNDQ
11
11
8
11
11
8
16
16
16
16
256K
(x 16)
4096
4096
4096
4096
R
MEMORY CELL
ARRAY
BANK 0
SENSE AMP I/O GATE
BANK CONTROL LOGIC
ROW
ADDRESS
BUFFER
FUNCTIONAL BLOCK DIAGRAM
相關PDF資料
PDF描述
IS42S32400A-7TI 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM
IS42S32400A-7TL 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM
IS61C256AH-8J x8 SRAM
IS61C256AH-8N x8 SRAM
IS61C256AH-8T x8 SRAM
相關代理商/技術參數
參數描述
IS42S32400A-7TI 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM
IS42S32400A-7TL 制造商:Integrated Silicon Solution Inc 功能描述:
IS42S32400A-7TLI 制造商:Integrated Silicon Solution Inc 功能描述:
IS42S32400B 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:4Meg x 32 128-MBIT SYNCHRONOUS DRAM
IS42S32400B-6B 制造商:Integrated Silicon Solution Inc 功能描述:IC SDRAM 128MBIT 166MHZ 90FBGA
主站蜘蛛池模板: 安义县| 伊宁市| 河曲县| 贡山| 龙江县| 锡林浩特市| 孟津县| 钟山县| 洛川县| 滨州市| 虎林市| 融水| 林州市| 沽源县| 台山市| 武安市| 横峰县| 南木林县| 新沂市| 武宣县| 万盛区| 台北县| 海门市| 阿拉善右旗| 什邡市| 天柱县| 会东县| 白朗县| 岐山县| 桂平市| 河池市| 天台县| 鄂尔多斯市| 乐平市| 丰台区| 仲巴县| 双城市| 左云县| 双桥区| 浮山县| 巴东县|