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參數資料
| 型號： | IS43R16800A1-5TL |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 8Meg x 16 128-MBIT DDR SDRAM |
| 中文描述： | 8M X 16 DDR DRAM, 0.65 ns, PDSO66 |
| 封裝： | LEAD FREE, PLASTIC, TSOP2-66 |
| 文件頁數： | 1/72頁 |
| 文件大小： | 2174K |
| 代理商： | IS43R16800A1-5TL |
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Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/17/06
1
ISSI
IS43R16800A1
Copyright 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
FEATURES
Clock Frequency: 200, 166 MHz
Power supply (V
DD
and V
DDQ
): 2.6V
SSTL 2 interface
Four internal banks to hide row Pre-charge
and Active operations
Commands and addresses register on positive
clock edges (CK)
Bi-directional Data Strobe signal for data cap-
ture
Differential clock inputs (CK and
CK
) for
two data accesses per clock cycle
Data Mask feature for Writes supported
DLL aligns data I/O and Data Strobe transitions
with clock inputs
Programmable burst length for Read and Write
operations
Programmable CAS Latency (2.5, 3 clocks)
Programmable burst sequence: sequential or
interleaved
Burst concatenation and truncation supported
for maximum data throughput
Auto Pre-charge option for each Read or Write
burst
4096 refresh cycles every 64ms
Auto Refresh and Self Refresh Modes
Pre-charge Power Down and Active Power
Down Modes
Lead-free Availability
8Meg x 16
128-MBIT DDR SDRAM
PRELIMINARY INFORMATION
APRIL 2006
IS43R16800A1
1M x16x8 Banks
V
DD
: 2.6V
V
DDQ
: 2.6V
66-pin TSOP-II
DEVICE OVERVIEW
I
SSI’s 128-Mbit DDR SDRAM achieves high-speed data
transfer using pipeline architecture and two data word
accesses per clock cycle. The 134,217,728-bit memory
array is internally organized as four banks of 32M-bit to
allow concurrent operations. The pipeline allows Read
and Write burst accesses to be virtually continuous, with
the option to concatenate or truncate the bursts. The
programmable features of burst length, burst sequence
and CAS latency enable further advantages. The device
is available in 16-bit data word size. Input data is regis-
tered on the I/O pins on both edges of Data Strobe
signal(s), while output data is referenced to both edges of
Data Strobe and both edges of CK. Commands are
registered on the positive edges of CK. Auto Refresh,
Active Power Down, and Pre-charge Power Down modes
are enabled by using clock enable (CKE) and other
inputs in an industry-standard sequence. All input and
output voltage levels are compatible with SSTL 2.
KEY TIMING PARAMETERS
Parameter
-5
Unit
DDR400
Clock Cycle Time
CAS
Latency = 3
CAS
Latency = 2.5
CAS
Latency = 2
5
6
—
ns
ns
ns
Clock Frequency
CAS
Latency = 3
CAS
Latency = 2.5
CAS
Latency = 2
200
166
—
MHz
MHz
MHz
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相關代理商/技術參數 |
參數描述 |
|---|---|
| IS43R16800A-5T | 功能描述:動態隨機存取存儲器 128M 2.5v 8Mx16 400MHz RoHS:否 制造商:ISSI 數據總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲容量:16 MB 最大時鐘頻率: 訪問時間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube |
| IS43R16800A-5TL | 功能描述:動態隨機存取存儲器 128M 2.5v 8Mx16 400MHz RoHS:否 制造商:ISSI 數據總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲容量:16 MB 最大時鐘頻率: 訪問時間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube |
| IS43R16800A-5TL-TR | 功能描述:動態隨機存取存儲器 128M 2.5v 8Mx16 400MHz RoHS:否 制造商:ISSI 數據總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲容量:16 MB 最大時鐘頻率: 訪問時間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube |
| IS43R16800A-5T-TR | 功能描述:動態隨機存取存儲器 128M 2.5v 8Mx16 400MHz RoHS:否 制造商:ISSI 數據總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲容量:16 MB 最大時鐘頻率: 訪問時間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube |
| IS43R16800A-6 | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:8Meg x 16 128-MBIT DDR SDRAM |
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